We present the technology steps to integrate an Echelle grating in the process flow of silicon-organic hybrid (SOH) modulators or related active devices. The CMOS-compatible process flow on SOI substrates uses a mix of optical i-line lithography and electron beam lithography (EBL). High speed optical data communication depends on wavelength divisions multiplexing and de-multiplexing devices like Echelle gratings. The minimum feature sizes vary from device to device and reach down to 60 nm inside a modulator, while the total area of a single Echelle grating is up to several mm2 of unprocessed silicon. Resist patterning using a variable shape beam electron beam pattern generator allows high resolution. An oxide hard mask is deposited, patterns are structured threefold by EBL and are later transferred to the silicon. We demonstrate a 9-channel multiplexer featuring a 2 dB on-chip loss and an adjacent channel crosstalk better than -22 dB. Additionally a 45-channel Echelle multiplexer is presented with 5 dB on chip loss and a channel crosstalk better than -12 dB. The devices cover an on-chip area of only 0.08 mm2 and 0.5 mm2 with a wavelength spacing of 10.5 nm and 2.0 nm, respectively.
Targeting mass production of nanostructures, nanoimprint lithography (NIL) is one of the most cost-effective ways to do
so. One of the most critical topics is the pattern quality of the imprint master template. Therefore the new Vistec SB4050
VSB e-beam writer has been evaluated regarding its capability for state-of-the-art NIL template and DOE making.
Equipped with a new air bearing stage the tool can expose a wide variety of substrates including large and heavy ones.
For 9035 substrates a placement accuracy of 9nm (3sigma) as well as an overlay accuracy of 7nm (3sigma) with a mean
error below 2nm has been achieved. Targeting for minimum feature size, a resolution below 30nm has been achieved for
both, dense lines and holes pattern even using CAR. In addition, 3D structuring capability has been proved by applying
GenISys’ Layout Beamer calibrated for an appropriate negative tone resist. Further investigation has been done on shot
count optimization regarding circular holes respective pillars. Using a feature size dependent segmentation, writing time
reduction could be achieved keeping the original feature shape.
Besides screening of typical tool parameter an application driven evaluation has been done by fabricating different type
of templates based on silicon and quartz. 2D and 3D features have been realized. Furthermore holograms have been
fabricated and proved for their performance by optical measurements.
For nearly all relevant applications of e-beam lithography the resolution and pattern quality requirements are
approaching or exceeding the limits of the available process. On one hand, for shrinking feature dimensions, the e-beam
proximity effect and process effects such as photo acid diffusion limit the pattern contrast and process window. On the
other hand, e-beam process related parasitic effects such as shot noise, fogging, developer loading, heating, charging, and
inhomogeneous bake introduce some significant errors. Even though e-beam tool and process tool suppliers continue to
implement new or improve current strategies to avoid or correct these effects, the amount of residual errors requires
some reasonable e-beam process window, in particular for high end applications.
For some patterns the undersize-overdose approach (SIZE) improves the pattern fidelity and process window. However,
for patterns with high fill factors this approach increases the overall deposited electron dose, which due to the increased
backscattering diminishes or even eliminates the advantages. The geometrically induced dose correction (GIDC) method
overcomes this issue by combining the SIZE concept with a short range framing technique, which reduces the deposited
dose in large filled pattern areas.
This paper provides a comparison of the standard, SIZE, and GIDC correction approaches for 1D test patterns as well as
production patterns. For a broad comparison, patterns were printed onto negative and positive chemically amplified
resists and on wafer and mask substrates using a Vistec SB352HR variable shape e-beam writer. Both wafers were also
etched.
The outcome of the study is that the SIZE and GIDC approaches often outperform the standard proximity effect
correction. For dense patterns, GIDC still provides a better pattern quality and process window, while the SIZE approach
suffers from the increased overall deposited electron dose and clearly falls behind GIDC in terms of process window.
Further it was shown that the lowering of the dose in inner areas due to GIDC does not impact the etch resistance.
Organic electronics are gaining increasing interest and attention in electronic device fabrication due to cost advantages
and low process manufacturing temperatures, which allow the use of mechanically-flexible polymeric substrates.
Different patterning techniques for Organic Thin Film Transistors (OTFT) with sub μm channel length are currently
under investigation like inkjet-printing, nanoimprint, optical- and e-beam lithography. This paper describes a new
approach for OTFT fabrication by device patterning with Si stencil lithography. This high resolution shadow mask
technique allows the parallel patterning of sub μm features without the use of photosensitive resists or chemical solvents,
which could lead to a degradation of the sensitive organic semiconductor layer. At first the device pattern is etched into a
thin Si membrane layer, creating design-specific sub μm features. Subsequent this stencil mask is aligned and clamped to
the substrate and material is deposited through the stencil apertures forming the desired device pattern onto the substrate.
By repeating this sequence with different deposition materials a classical top contact TFT architecture with a gate
electrode, gate dielectric, organic semiconductor and source drain contacts can be achieved.
A detailed evaluation study has been performed with respect to the suitability of projection electron and ion multi-beam
lithography for the fabrication of leading-edge complex masks. The study includes recent results as obtained with
electron and ion multi-beam proof-of-concept systems with 200x reduction projection optics where patterns are
generated on substrates using a programmable aperture plate system (APS) with integrated CMOS electronics,
generating several thousands of well defined beams in parallel. A comparison of electron and ion projection multi-beam
writing is provided, in particular with respect to the suitability to expose non-chemically amplified resist (non-CAR)
materials. The extendibility of projection multi-beam technologies for 16nm hp, 11nm hp and 8nm hp mask nodes is
discussed as well as for wafer direct write for 22nm hp and below.
At the EMLC 2009 in Dresden the data preparation package ePLACE was already presented. This package has been
used for quite different applications covering mask write, direct write and special applications. In this paper we will
disclose results achieved when using the ePLACE package for processing of layout data of immediate interest. During
the evaluation phase of the new solution we could benefit from broad experience we collected over many years with the
fracture performance of the MGS software, which is one core element of today's ePLACE package.
A key interest of this paper is the investigation of the scalability of computing solutions as a cost-effective approach
when processing huge data volumes with the new solution. This is reflected against current state-of-the-art data processing
tasks being part of both mask write and direct write applications.
Furthermore, we evaluated visualization and simulation possibilities of the ePLACE package with respect to its use with
latest layouts in various applications.
The improved performance of the data preparation package including its adaptation to new e-beam lithography options,
as, for instance, the incorporation of the cell projection capability or the newly developed Multi Shaped Beam (MSB)
technology, will be also discussed.
As an example the matching of the data path with a Vistec SB3055 will be outlined. Processing of Design For E-Beam
(DFEB) data (including cell contents) and their conversion to real exposure data is reported. The advantages of the
parallel use of standard shaped beam und cell projection technologies are highlighted focussing on latest writing time
yields achieved when applying the CP feature.
Step and Flash Imprint involves the field-by-field deposition and exposure of a low viscosity resist deposited by
jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the
relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation,
and then the mask is removed leaving a patterned solid on the substrate. Compatibility with existing CMOS processes
requires a mask infrastructure in which resolution, inspection and repair are all addressed. The purpose of this paper is
to understand the progress made in inspection and repair of 1X imprint masks
A 32 nm programmed defect mask was fabricated. Patterns included in the mask consisted of an SRAM Metal 1
cell, dense lines, and dense arrays of pillars. Programmed defect sizes started at 4 nm and increased to 48 nm in
increments of 4 nm. These defects were then inspected using three different electron beam inspection systems. Defect
sizes as small as 8 nm were detected, and detection limits were found to be a function of defect type. Both subtractive
and additive repairs were attempted on SRAM Metal 1 cells. Repairs as small as 32nm were demonstrated, and the
repair process was successfully tested for several hundreds of imprints.
A mask patterning process based on proton multi-beam exposure in combination with Opaque-Molybdenum-Over-Glass
(OMOG) hard mask blank material has been developed. As non-chemically amplified resist, HSQ has been selected.
Using the IMS Nanofabrication proof of concept proton Multi Beam System which is designed for 43,000 programmable
ion beams, an acceptable exposure dose of around 25μC/cm2 has been determined for 10 keV protons. Assessment of the
process flow has been done in terms of dose latitude, LER, LWR, CD variation, and resolution capability.
KEYWORDS: Semiconducting wafers, Lithography, Electron beams, Electrodes, Prototyping, Electron beam lithography, Electron beam direct write lithography, Silicon, Optical alignment, Photomasks
Projection Mask-Less Lithography (PML2) is a potentially cost-effective multi electron-beam
solution for the 22 nm half-pitch node and beyond. PML2 is targeted on using hundreds of
thousands of individually addressable electron-beams working in parallel, thereby pushing
the potential throughput into the wafers per hour regime. With resolution potential of < 10
nm, PML2 is designed to meet the requirements of several upcoming tool generations.
In the UV-NIL template fabrication sequence usually four 65×65mm2 templates are fabricated at once using a 6025 mask
blank. After finishing all patterning processes and the etching of the imprint pedestals the templates are separated by
dicing and polishing. This technique offers the advantage to use standard mask tools for the majority of the production
steps. In order to check the imprint pattern on the mask CD measurements of quartz features are necessary. To control
the fabrication process more effectively the additional measurement of resist features would be helpful. When the
template is used for imprinting, repeated cycles of anti-adhesion layer deposition and cleaning after multiple imprints
might change the CD of the quartz features. The metrology steps have to be performed on 1X features and are therefore
more challenging, compared to those for 4X photomasks. For this purpose we evaluated the capability of Vistec's CDSEM
LWM90xx for line-width measurements of nanoimprint templates. After optimization of hardware and software
settings, the measurement capability for different feature sizes has been characterized. Finally, the evaluated results have
been compared with the ITRS requirements for the 22nm node in order to address possible future needs.
KEYWORDS: Etching, Electron beam lithography, Line edge roughness, Photoresist processing, Electron beams, Ion beams, Photomasks, Line width roughness, Ions, Nanofabrication
Decreasing throughput of high-end pattern generators and insufficient line edge roughness (LER) of chemically
amplified resists (CAR) might become limitations for future mask making. An alternative could be the introduction of
less sensitive resists, linked to a turning away from today's electron beam pattern generators. Moderate exposure doses
of around 25μC/cm2 could be achieved for non-CAR materials like HSQ by the use of 10keV protons. Targeting
optimized absorber performance, Shin-Etsu has developed an Opaque-molybdenum-over-glass (OMOG) material,
designed for 32mn mask technology and beyond. This hard mask concept allows using thin resist layers, as required by
an ion beam exposure. Goal of this work was to assess a HSQ based non-CAR process using a multiple ion beam pattern
generator including subsequent transfer into the absorber by dry etch processes. Proton exposures have been done on the
IMS Nanofabrication proof of concept tool which is designed for 40,000 programmable ion beams. For comparison, an
electron based reference process has been set up in parallel to the proton multi-beam approach. Hard mask opening and
subsequent absorber etching have been accomplished in a state of the art mask etcher. Assessment of the process flow
has been done in terms of feature profile, LER and resolution capability.
Two main challenges of future mask making are the decreasing throughput of the pattern generators and the insufficient
line edge roughness of the resist structures. The increasing design complexity with smaller feature sizes combined with
additional pattern elements of the Optical Proximity Correction generates huge data volumes which reduce
correspondingly the throughput of conventional single e-beam pattern generators. On the other hand the achievable line
edge roughness when using sensitive chemically amplified resists does not fulfill the future requirements. The
application of less sensitive resists may provide an improved roughness, however on account of throughput, as well. To
overcome this challenge a proton multi-beam pattern generator is developed [1]. Starting with a highly parallel broad
beam, an aperture-plate is used to generate thousands of separate spot beams. These beams pass through a blanking-plate
unit, based on a CMOS device for de-multiplexing the writing data and equipped with electrodes placed around the
apertures switching the beams "on" or "off", dependent on the desired pattern. The beam array is demagnified by a 200x
reduction optics and the exposure of the entire substrate is done by a continuous moving stage.
One major challenge is the fabrication of the required high aspect deflection electrodes and their connection to the
CMOS device. One approach is to combine a post-processed CMOS chip with a MEMS component containing the
deflection electrodes and to realize the electrical connection of both by vertical integration techniques. For the evaluation
and assessment of this considered scheme and fabrication technique, a proof-of-concept deflection unit has been realized
and tested. Our design is based on the generation of the deflection electrodes in a silicon membrane by etching trenches
and oxide filling afterwards. In a 5mm x 5mm area 43,000 apertures with the corresponding electrodes have been
structured and wired individually or in groups with aluminum lines. The aperture-plate for shaping the beams has been
aligned and mounted on top of the blanking-plate. Afterwards this sandwich has been fixed on a base-plate with a pin
plug as interface. The electrical connection has been performed with a standard chip bonding process to the aluminum
pads on the blanking-plate. Finally, the proof-of-concept deflection unit was evaluated in a test bench. The results of
electrical- and exposure tests are presented and discussed in detail.
Two essential process steps of the template fabrication chain are inspection and repair. The widely introduced gas
assisted e-beam etching and deposition technique for mask repair offers crucial advantages, especially regarding the
resolution capability. We started the evaluation of a new e-beam repair test stand based on the Zeiss MeRiT technology
for UV-NIL template repair. For this purpose, templates with programmed defects of different shapes and sizes have
been designed and fabricated. The repair experiments were focused on the development of recipes for quartz etching and
deposition specifically tailored for NIL repair requirements Both, clear and opaque programmed defects have been
repaired and the results have been analyzed. After recipe optimization, templates with repaired programmed defects have
been imprinted on a Molecular Imprints Imprio 250 tool. By comparing template and imprint results we investigated the
repair capability.
With the willingness of the semiconductor industry to push manufacturing costs down, the mask
less lithography solution represents a promising option to deal with the cost and complexity concerns
about the optical lithography solution. Though a real interest, the development of multi beam tools still
remains in laboratory environment. In the frame of the seventh European Framework Program (FP7), a
new project, MAGIC, started January 1st 2008 with the objective to strengthen the development of the
mask less technology. The aim of the program is to develop multi beam systems from MAPPER and
IMS nanofabrication technologies and the associated infrastructure for the future tool usage. This paper
draws the present status of multi beam lithography and details the content and the objectives of the
MAGIC project.
A dual damascene template fabrication process has been developed, which enables the structuring of high-resolution,
high-aspect pillars on top of lines. Based on this technology templates with three different designs have been fabricated
and characterized. Two templates are dedicated for an assessment of the fabrication process using a regular test design
on one hand and an arbitrary CMOS design on the other hand. With the third template via chains shall be later realized as
demonstrator for electrical tests. The templates have been imprinted in resist and sacrificial material on an Imprio 55 and
an Imprio 100 tool. The usability of each fabricated template could be confirmed for the specific application. For the
template manufacturing a Vistec variable shape e-beam (VSB) writer SB352HR and appropriate positive-tone and
negative-tone chemically amplified resists (CAR) have been used.
Projection Mask-Less Lithography (PML2) is a potentially cost-effective multi electron-beam solution for the 32nm-node
and beyond. PML2 is targeted on using hundreds of thousands of individually addressable electron-beams working
in parallel, thereby pushing the potential throughput into the wafers per hour regime. With resolution limits <10nm,
PML2 is designed to meet the requirements of several upcoming tool generations.
A PML2 proof-of-concept setup was realized within the framework of the European RIMANA project. It contains all
crucial components of a full-fledged PML2 tool and unambiguously demonstrates the operability of multi electron-beam
projection optics with 200x reduction. In the PML2 proof-of-concept system more than 2000 switchable beams are
generated by a programmable aperture plate system (APS) and projected onto wafer level with 200x demagnification.
Current density (~2 A/cm2) and total current (~10 pA) of each beam are the same as in future PML2 tools, resulting in a
calculated base resolution below 10nm. The PML2 proof-of-concept column has been successfully tested using
resolution templates, verifying 200x reduction and the predicted 22nm hp resolution capability. Furthermore, first
custom designed 32nm hp structures were printed into resist coated Si wafers using an APS test-unit.
Based on the inputs obtained by the PML2 proof-of-concept system and detailed electron-optical calculations, a fully
industry-compatible PML2 Alpha-tool will be realized within the European MAGIC project. Together with the
infrastructure developed within MAGIC, this PML2 Alpha-tool promises to herald the introduction of mask-less
lithography into the industrial environment.
Line edge roughness (LER) and substrate resist interaction of chemically amplified resists (CAR) might be limitations for future mask making. An alternative solution could be the direct patterning of a thin hard mask on top of an absorber using a multiple ion beam pattern generator. Goal of this work was to assess a resistless hard mask structuring by direct patterning and a subsequent transfer into chrome by a dry etch process. Hard mask structuring has been done on the IMS Nanofabrication proof of concept tool which is designed for 40,000 multi-beam operations. For comparison to the resistless approach, a resist based stack patterning has been set up. Hard mask opening and subsequent chrome etching have been accomplished in a state of the art mask etcher. The assessment of both process schemes has been done in terms of feature profile and resolution capability. Finally, throughput estimation for a future production tool, operating with precursor gases and 1.000.000 ion beams has been calculated.
A 3D template fabrication process has been developed, which enables the generation of high resolution, high aspect
pillars on top of lines. These templates will be used to print both vias and metal lines at once for the dual damascene
technology. Due to the complexity of state of the art CMOS designs only a variable shape e-beam (VSB) writer
combined with chemically amplified resists (CAR) can be considered for the patterning process. We focused our work
especially on the generation of high aspect pillars with a diameter below 50nm and the development of suitable overlay
strategies for getting a precise alignment between the two template tiers. In this context we investigated the influence of
exposure strategies on the overlay result across the entire imprint area of 25mm × 25mm. Finally, we realized templates
according to the MII standard with different test designs and confirmed printability of one of them on a MII tool.
NIL technique enables an easy replication of three dimensional patterns. Combined with a UV printable low-k material the NIL lithography can dramatically simplify the dual damascene process. Goal of this work was to develop a template process scheme which enables the generation of high resolution pillars on top of corresponding lines for direct printing of later vias and metal lines. The process flow is based on conventional 6025 photomask blanks. Exposure was done on a variable shaped e-beam writer Vistec SB350 using a sample of an advanced negative tone CAR and Fujifilm pCAR FEP171 for the first and the second layer, respectively. Chrome and quartz etching was accomplished in an Oerlikon mask etcher Gen III and Gen IV. Assessment of the developed template process was done in terms of overlay accuracy, feature profile and resolution capability depending on aspect ratio and line duty cycle. Finally the printability of 3D templates fabricated according the developed process scheme was proved.
In the framework of the European EXTUMASK project, the Advanced Mask Technology Center in Dresden (AMTC) has established in close collaboration with the Institute of Microelectronics in Stuttgart (IMS-Chips) an integrated mask process suited to manufacture EUV masks for the first full field EUV scanner, the ASML α-demo tool. The first product resulting from this process is the ASML set-up mask, an EUV mask designed to realize the tool set-up.
The integrated process was developed based on dummy EUV blank material received from Schott Lithotec in Meiningen (Germany). These blanks have a TaN-based absorber layer and a SiO2 buffer layer. During process development the e-beam lithographic behaviour as well as the patterning performance of the material were studied and tuned to meet first EUV mask specifications.
For production of the ASML set-up mask the new process was applied to a high performance EUV blank from Schott Lithotec. This blank has absorber and buffer layers identical to the dummy blanks but a multilayer is embedded which is deposited on an LTEM substrate. The actinic behaviour of the multilayer and the flatness of the substrate were tuned to match the required mask specifications. In this article we report on the development of the mask manufacturing process and show performance data of produced EUV full field scanner masks. Thereby, special attention is given to the ASML set-up mask.
A resolution of 45nm dense lines has been be realized in a 100nm thick commercial available positive tone chemically amplified resist (pCAR) using the Leica SB350 variable shaped beam writer. On the basis of this resist process and by optimization of photomask blank material as well as by adaptation of chrome and quartz etching processes, a nanoimprint template technology has been developed which enables patterning of 50nm dense lines. The sensitivity of the selected pCAR as well as the performance of the implemented dynamical stage control of the Leica pattern generator, facilitates an acceptable throughput even for complex pattern. We characterized the templates in terms of feature profile, CD linearity and pattern fidelity. The final imprinting of different pattern proved the applicability of the manufactured stamps for the nanoimprint technology.
Continuous reduction of feature size in semiconductor industry and manufacturing integrated circuits at low costs requires new and innovative technology to overcome existing limitations of optics. Tremendous progress in key areas like EUVL light source technology and manufacturing technology of EUVL masks with low defect rates have been made recently and EUVL is the leading technology capable to be extended so Moore's law, the shrinkage of IC critical features, can continue to be valid. SCHOTT Lithotec has introduced all relevant technology steps to manufacture EUV mask blanks, ranging from Low Thermal Expansion Material (LTEM) with high quality substrate polishing to low defect blank manufacturing. New polishing and cleaning technologies, improved sputter technology and updated metrology enable us to routinely produce EUVL mask blanks meeting already many of the roadmap requirements. Further R&D is ongoing to path the way to the production of EUV blanks which meet all requirements.
An important focus of this paper is to present the recent results on LTEM substrates, which include defect density, roughness and flatness simultaneously, as well as EUVL multilayer properties such as defect density, optical properties like reflectivity and uniformity in the EUV range and optical resistance to cleaning steps. In addition the design of EUVL absorber material will be discussed, including optical performance at EUV wavelength and its contrast behavior.
Finally, IMS Chips has developed the dry etch process of these EUV Mask Blanks by optimizing etch selectivities, profiles and etch bias. Results on CD uniformity, linearity and iso/dense bias will be presented.
The present paper will show an approach for a local and global stress determination by the application of a Leica LMS IPRO II mask registration tool. Changes in placement due to a full or partial layer removal on single materials as well as material stacks with respect to a reference grid were determined. Simulation using finite element modeling was conducted to calculate stress values from the placement information. Finally, an estimate was made of the acceptable stress level for a sample design to meet placement requirements for future lithography nodes.
An initial Nanoimprint template manufacturing process using a state-of-the-art mask front end line has been developed. The process flow is based on conventional 6025 photomask blanks and known basic process steps for chrome and quartz etching. While these etching processes have been slightly adapted, a comprehensive investigation of chemically amplified resists for this purpose was done. We were able to identify a pre-commercial pCAR enabling to approach the 50nm dense line resolution using the Leica SB350 variable shaped beam e-beam writer. We characterized profile, CD-linearity, CD-uniformity and placement accuracy of the nanoimprint templates. The final imprinting of different pattern proved the applicability of the manufactured stamps for the nanoimprint technology.
Extreme Ultraviolet Lithography (EUVL) is the favourite next generation lithography candidate for IC device manufacturing with feature sizes beyond 32nm.
Different stacks and manufacturing concepts have been published for the fabrication of the reflective EUVL masks.
Patterning processes for two different absorber-buffer combinations on top of the reflective multi layer mirror have been developed. A TaN/SiO2 absorber-buffer stack was provided by supplier A and TaBN/Cr by supplier B. In addition both absorbers were covered by an anti reflective coating (ARC) layer. An e-beam patterned 300nm thick film of Fuji FEP171 was used as resist mask.
We optimized the etching processes for maximum selectivities between absorber, buffer and capping layers on the one hand and rectangular profiles and low etch bias on the other hand. While both TaN based absorbers have been dry etched in an UNAXIS mask etcher III, wet and dry etch steps have been evaluated for the two different buffer layers. The minimum feature size of lines and holes in our test designs was 100nm.
After freezing the processes a proximity correction was determined considering both, the influence of electron scattering due to e-beam exposure and the influence of the patterning steps. Due to the correction an outstanding linearity and iso/dense bias on different test designs was achieved.
Various masks for printing experiments at the small-field Micro Exposure Tool (MET) in Berkeley and the fabrication of the ASML α-tool setup mask within the European MEDEA+ EXTUMASK project were done using the developed processes.
Finally, we will compare and discuss the results of the two stack approaches.
For the new Schott EAPSM Material, comprising a Ta/SiO2/Cr stack, a patterning process has been developed.
The material offers the advantage of an independent adjustment of phase shift and transmission and is applicable for different wavelengths. Because of very homogenous Ta and SiO2 films and perfect etch selectivities it has been achieved a phase shift uniformity of 1.1° and a tight transmission deviation of 0.34% (absolute) across the entire mask.
First dry etch process development has been focused on profiles and selectivities. The influence of process parameters on sidewall angle, profile bow, resist loss and Cr loss of the three patterning steps are shown. We have achieved excellent selectivities and a final sidewall angle of > 88°.
The aerial image contrast of the first test plate is comparable to known attenuated phase shift material.
KEYWORDS: Critical dimension metrology, Scanning electron microscopy, Monte Carlo methods, Extreme ultraviolet, Photomasks, Detection and tracking algorithms, Silicon, Electron beams, Extreme ultraviolet lithography, Signal detection
For extreme ultraviolet lithography (EUVL) the absorber binary mask is until now the most promising mask type. Since at EUV only reflective masks are possible, EUVL will introduce new materials for mask manufacturing. In addition it is likely that the pattern of an EUV mask will consist of a structured double layer system. Therefore, mask CD-SEM metrology for EUVL has to deal with the contrast of rather new materials and has to face a more complex mask pattern topography situation. Using a Monte Carlo model, we simulate the SEM-signals emerging from a given EUV mask pattern topography while scanned by the electron beam of a SEM. The simulation is tuned to closely match the experimental situation of a commercial CD-SEM. Generated SEM images are analyzed by means of a commercial CD-algorithm and a peak detection CD-algorithm. Knowing the exact pattern shape that are fed into the simulation, we determine the effect of specific pattern profile changes on SEM-signal and algorithm specific CD.
Several masks have been fabricated and exposed with the small-field Micro Exposure Tool (MET) at the Advanced Light Source (ALS) synchrotron in Berkeley using EUV radiation at 13.5 nm wavelength. Investigated mask types include two different absorber masks with TaN absorber as well as an etched multilayer mask. The resulting printing performance under different illumination conditions were studied by process window analysis on wafer level. Features with resolution of 60 nm and below were resolved with all masks. The TaN absorber masks with different stack thicknesses showed a similar size of process window. The differences in process windows for line patterns were analyzed for 60 nm patterns. The implications on the choice of optimum mask architecture are discussed.
Recently developed positive tone CARs (pCAR) and negative tone CARs (nCAR) have been evaluated for mask making using a 50kV e-beam pattern generator. We determined a screening method considering the most important parameters for example resolution, profile, delay influences, line edge roughness (LER), which was identically applied for all investigated resist samples. The screening was accomplished on 6025 chrome blanks using a state-of-the-art mask line. Some of the investigated resists have shown promising progress in terms of straight profile, of reduced footing, of lower line edge roughness and of an almost insensitive influence of the post exposure delay. Unfortunately, all the improvements were not unified in one sample.
Extreme Ultraviolet Lithography (EUVL) is the favourite next generation lithography candidate for IC device manufacturing with feature sizes beyond 32nm. The SiO2 buffer dry etching is a crucial step in the manufacture of the EUV mask due to stringent CD and reflectance requirements. In contrast to conventional chromium absorber layers new absorber materials e.g. TaN require an adjustment of the SiO2 buffer etch chemistry and process parameters to avoid a strong influence on the initial absorber profile and thickness. We have developed a SiO2 buffer dry etch process that uses the structured TaN absorber as masking layer. A laser reflectometer was used during the SiO2 dry etch process for process control and endpoint detection. Different dry etch processes with SF6/He, CF4 and CHF3/O2 etch chemistry have been evaluated and compared with regard to TaN- and SiO2- etch rate, TaN- and SiO2 etch profile and Si capping layer selectivity. We focused our work on minimum feature sizes and simultaneous etching of different line (e.g. dense- and isolated lines) and hole patterns. Line and contact hole structures with feature sizes down to 100nm have been realized and characterized in a SEM LEO 1560. The whole mask patterning process was executed on an advanced tool set comprising of a Leica SB 350 variable shaped e-beam writer, a blank coater Steag HamaTech ASR5000, a developer Steag HamaTech ASP5000 and a two chamber UNAXIS mask etcher III.
Three different architectures were compared as candidates for EUV lithography masks. Binary masks were fabricated using two different stacks of absorber materials and using a selective etching process to directly pattern the multilayer of the mask blank. To compare the effects of mask architecture on resist patterning, all three masks were used to print features into photoresist on the EUV micro-exposure tool (MET) at Lawrence Berkeley National Laboratory. Process windows, depth of focus, mask contrast at EUV, and horizontal and vertical line width bias were use as metrics to compare mask architecture. From printing experiments, a mask architecture using a tantalum nitride absorber stack exhibited the greatest depth of focus and process window of the three masks. Experimental results obtained using prototype masks are discussed in relation to simulations. After accounting for CD biasing on the masks, similar performance was found for all three mask architectures.
EUV Lithography requires high end quality defect free layers from the backside coating to the absorber stack. Low thermal expansion materials (LTEM) substrates with super flat surfaces are already available with low defect backside coating for E-Chuck technology. The multilayer stack is well developed from a physical point of view and major effort relies nowadays on the layer defectivity. On the other hand, absorber stack becomes one of the main challenges in terms of stress, optical behavior for ultraviolet wavelengths and dry etching behavior. Schott Lithotec is currently developing absorber stack solutions that will fulfill the requirements of next generation lithographies. There are several options for achieving the mechanical, optical and chemical specs for buffer layers and absorber coatings. Some of them are already integrated in our production processes. Buffer layers were evaluated and reach almost the physical and chemical level necessary to fit with the mask processing. TaN based absorber coatings were designed and deposited by an ion beam sputter tool optimized for low defect deposition (LDD-IBS). The chemical composition of our layer and its manufacturing process is already optimized to achieve high quality etching behavior. The current results of defect density for the absorber stack will be presented.
The combination of conductive topcoat ESPACER Z300 and positive tone CAR FEP171 was investigated in detail for the second level patterning of Alternating Aperture Phase Shift Masks (AAPSM) using e-beam lithography. Chrome load variations between 2 and 50% with the corresponding deviation of the second level pattern, homogeneously and unevenly distributed on the mask, had no significant impact on placement and overlay accuracy. No clear defect increasing could be measured when applying ESPACER top coat. The quartz etch selectivity of FEP171 was identically with the widely accepted laser resist IP3600 and a good etch depth linearity was achieved down to 200nm feature size. Finally, the performance of the developed process has been demonstrated on a 65nm node device design.
Optimized process parameters using the TOK OEBR-CAN024 resist for high chrome load patterning have been determined. A tight linearity tolerance for opaque and clear features, independent on the local pattern density, was the goal of our process integration work. For this purpose we evaluated a new correction method taking into account electron scattering and process influences. The method is based on matching of measured pattern geometry by iterative back-simulation using multiple Gauss and/or exponential functions. The obtained control function acts as input for the proximity correction software PROXECCO. Approaches with different pattern oversize and two Cr thicknesses were accomplished and the results have been reported. Isolated opaque and clear lines could be realized in a very tight linearity range. The increasing line width of small dense lines, induced by the etching process, could be corrected only partially.
Currently, EUV lithography targets for sub-50 nm features. These very small feature sizes are used for reflective illumination and impose great challenges to the mask maker since they do not allow a simple downscaling of existing technologies. New material combinations for absorber and buffer layer of EUV masks have to be evaluated and fundamental material limits have to be overcome. We report on optimized absorber-stack materials and compare in particular the performance of chrome and tantalum nitride for such small nodes. Tantalum nitride shows similar or even better properties than standard chrome, above all with respect to etch bias. Further investigations have to be done but this material is a promising candidate for feature sizes in the sub-50 nm range.
The aim is to apply e-beam lithography for second level imaging of Alternating Phase Shift Masks (altPSM) in the 65 nm node and below. Difficulties due to charging effects arise when exposing areas where the chromium absorber has been cleared away. In order to achieve correct pattern placement, the commercial water-soluble conductive ESPACER 300Z top coat from Showa Denka is applied in combination with chemically amplified resist of type FEP171. The paper describes the method and algorithm to test the efficacy of the material and the technological steps taken to avoid or reduce charge effects. The obtained overlay accuracy proves the ESPACER/FEP171 combination a promising approach for future altPSM manufacturing.
When e-beam lithography is applied for second level imaging of Alternating Phase Shift Masks charging effects on the cleared chrome absorber induces placement, overlay and pattern distortion of the second layer. The water soluble conductive to coat Showa Denko ESPACER 300Z has been evaluated in combination with the chemically amplified resist FEP171 for a charging eliminating patterning solution. Application of ESPACER on top of FEP171 kept the resist performance unchanged. Sensitivity, profile, resolution, CD-uniformity and post exposure delay of FEP171 have been investigated and no influence of ESPACER was detected. The bilayer system ESPACER and FEP171 was used for the second patterning of an altPSM test design and the technology performance was characterized. No difference has been figured out between placement of the second level and placement on a non-structured chrome layer. The achieved overlay accuracy proves the ESPACER/FEP171 combination as a promising approach for future altPSM manufacturing.
A mask patterning technology for the 90nm technology node has been developed using the FujifilmARCH resist FEP171 and the state-of-the-art mask making tools SteagHamaTech mask coater ASR5000, Leica 50kV variable shaped e-beam writer SB350, SteagHamaTech developer ASR5000 and UNAXIS Mask Etcher III. A resist resolution of below 100nm dense lines and 150nm contact holes was demonstrated. The line width shrinking due to chrome etching varies between 25nm and 50nm per feature and a corresponding resolution of 125nm dense lines in a 105nm thick chrome absorber has been achieved. The global CD-uniformity with a 3σ of 7.7nm and a total range of 10.8nm met the requirements of the ITRS roadmap. The local uniformity with a 3σ of 3.8nm and a range of 5.6nm offers potential for future application of the Leica SB350. Applying of a new correction method taking electron scattering and process characeristics into account provides a linearity of 6.1nm. In addition, the line width of different featurees was kept in a range up to 12nm when the local pattern density was changed. The composite placement accuracy of 12nm fulfills already the requirements of the 65nm node. A special investigation proved the excellent fogging depression of the SB350.
Negative-tone chemically amplified resists MES-EN1G (JSR), FEN-270 (Fujifilm ARCH), EN-024M (TOK) and NEB-22 (Sumitomo) were evaluated for binary mask making. The investigations were performed on an advanced tool set comprising a 50kV e-beam writer Leica SB350, a Steag Hamatech hot/cool plate module APB5000, a Steag Hamatech developer ASP5000, an UNAXIS MASK ETCHER III and a SEM LEO1560 with integrated CD measurement option. We investigated and compared the evaluated resists in terms of resolution, e-beam sensitivity, resist profile, post exposure bake sensitivity, CD-uniformity, line edge roughness, pattern fidelity and etch resistance. Furthermore, the influence of post coating delay and post exposure delay in vacuum and air was determined.
Hans Loeschner, Gerhard Stengl, Herbert Buschbeck, A. Chalupka, Gertraud Lammer, Elmar Platzgummer, Herbert Vonach, Patrick de Jager, Rainer Kaesmaier, Albrecht Ehrmann, Stefan Hirscher, Andreas Wolter, Andreas Dietzel, Ruediger Berger, Hubert Grimm, Bruce Terris, Wilhelm Bruenger, Gerhard Gross, Olaf Fortagne, Dieter Adam, Michael Boehm, Hans Eichhorn, Reinhard Springer, Joerg Butschke, Florian Letzkus, Paul Ruchhoeft, John Wolfe
Recent studies have shown the utility of ion projection lithography (IPL) for the manufacturing of integrated circuits. In addition, ion projection direct structuring (IPDS) can be used for resistless, noncontact modification of materials. In cooperation with IBM Storage Technology Division, ion projection patterning of magnetic media layers has been demonstrated. With masked ion beam proximity techniques, unique capabilities for lithography on nonplanar (curved) surfaces are outlined. Designs are presented for a masked ion beam proximity lithography (MIBL) and masked ion beam direct structuring (MIBS) tool with sub-20-nm resolution capability within 88-mm□ exposure fields. The possibility of extremely high reduction ratios (200:1) for high-volume projection maskless lithography (projection-ML2) is discussed. In the case of projection-ML2 there are advantages of using electrons instead of ions. Including gray scaling, an improved concept for a ⩽50-nm projection-ML2 system is presented with the potential to meet a throughput of 20 wafers per hour (300 mm).
From detailed comparisons of stencil mask distortion measurements with Finite Element (FE) analyses the parameters of influence are well known. Most of them are under control of the mask manufacturer, such as the membrane stress level and the etching process. By means of FE analysis the different contributions may be classified. Some of the errors can be reduced if more stringent specifications of the SOI wafer are fulfilled, some of them may be reduced after pre-calculation. Reduction of the remaining placement errors can be achieved if specific means of an Ion Projection Lithography (IPL) tool are applied. These are mainly magnification and anamorphic corrections removing so-called global distortions. The remaining local distortions can be further reduced by applying the concept of thermal mask adjustment (THEMA).
Positive tone chemically amplified resists CAP209, EP012M (TOK), KRS-XE (JSR) and FEP171 (Fuji) were evaluated for mask making. The investigations were performed on an advanced tool set comprising of a Steag coater ASR5000, Steag developer ASP5000, 50kV e-beam writer Leica SB350, UNAXIS MASK ETCHER III , STS ICP silicon etcher and a CD-SEM KLA8100. We investigated and compared resolution, sensitivity, resist slope, dark field loss, CD-uniformity, line edge roughness, and etch resistance of the evaluated resists. Furthermore, the influence of post coating delay, post exposure delay and other process parameters on the resist performance was determined.
Hans Loeschner, Gerhard Stengl, Herbert Buschbeck, A. Chalupka, Gertraud Lammer, Elmar Platzgummer, Herbert Vonach, Patrick de Jager, Rainer Kaesmaier, Albrecht Ehrmann, Stefan Hirscher, Andreas Wolter, Andreas Dietzel, Ruediger Berger, Hubert Grimm, Bruce Terris, Wilhelm Bruenger, Dieter Adam, Michael Boehm, Hans Eichhorn, Reinhard Springer, Joerg Butschke, Florian Letzkus, Paul Ruchhoeft, John Wolfe
Recent studies carried out with Infineon Technologies have shown the utility of Ion Projection Lithography (IPL) for the manufacturing of integrated circuits. In cooperation with IBM Storage Technology Division the patterning of magnetic films by resist-less Ion Projection Direct Structuring (IPDS) has been demonstrated. With masked ion beam proximity techniques unique capabilities for lithography on non-planar (curved) surfaces are outlined. Designs are presented for a masked ion beam proximity lithography (MIBPL) exposure tool with sub - 20 nm resolution capability within 88 mmo exposure fields. The possibility of extremely high reduction ratios (200:1) for high-volume ion projection mask-less lithography (IP-ML2) is discussed.
Stencil masks, based on 150mm Si-wafers, with large diameter membrane fields have been fabricated for use in an ion projection lithography (IPL) tool. With a current membrane diameter of 126mm, the control of pattern placement is one of the major challenges. As the masks are produced by a wafer flow process, pattern distortions after membrane etch, caused by stiffness changes, have to be controlled. Additionally, stress inhomogenity resulting from SOI wafer blank fabrication, boron implantation and other process steps has to be addressed. These parameters will be discussed on a global and local scale. Results by both, experiments and FE modeling simulations are presented.
A short review of the current status of IPL stencil mask development is presented in this paper. Stencil masks based on 6' Si-wafer have been fabricated with a membrane diameter of 126 mm. With a typical membrane thickness of 3 micrometers , mechanical stability is a critical issue. The resulting placement errors have been measured using an LMS IPRO measurement tool and have been compared to Finite Element (FE) calculations simulating the fabrication process. Process-induced distortions can be predicted by FE calculations with an accuracy of up to 24 mm 3(sigma) . In addition to large circular membranes, an alternative geometry has been considered. Masks with a quadratic membrane area of 60 X 60 mm2 show IPDs of 3(sigma) equals 39 nm which are about 4 times smaller than those of large circular membranes. This result agrees well with predictions of FE calculations. In order to protect the Si-mask against ion bombardment, a protective carbon layer is deposited onto the membrane, thus preventing stress changes due to ion implantation. The current status of the carbon deposition process will also be addressed briefly.
Corresponding to characteristics and manufacturing processes of IPL stencil masks, requirements of used resist technologies are determined. Two thin layer imaging (TLI) techniques, the single layer top surface imaging (TSI) and the bilayer CARL (chemical amplification of resist line) have been investigated and compared for stencil mask making. Especially the process design of CARL is discussed in detail. Additionally, a possible process integration of the carbon layer, that is deposited on the stencil mask and protects the membrane against damaging due to ion bombardment, is presented. Finally, results of silicon etching and complete manufactured stencil masks using the developed resist technologies are demonstrated.
Stencil masks for Ion Projection Lithography (IPL) are manufactured in a SOI wafer flow process. They consist of a 3 micrometer thick stencil membrane coated by a 0.5 micrometer thick carbonic protection layer. For mask manufacturing, the key parameters which have to be kept under tight control in order to have a high yield are critical dimensions (CD), image placement and defect density. In order to control critical dimensions, the parameters determining CD have to be known in detail. E-beam writing, resist processing, silicon and carbon etching are main contributors. Their impact will be discussed. For CD measurement, different alternatives of tools, optical CD microscopes, AFM and SEM are discussed. Image placement is one of the most critical parameters for IPL stencil masks, as process-induced distortions occur and are to be corrected by a software using FE calculations. Masks usually are specified to 0 defects. Defect inspection results of IPL stencil masks of optical tools are presented, as well as results from e-beam inspection. In addition, defect management for stencil masks in general and cleaning techniques are discussed.
Ion Projection Lithography (IPL) requires stencil masks. These masks are manufactured in a SOI wafer flow process. This means that e-beam patterning and the pattern transfer in silicon is done on the bulk mask-wafer blank before the membrane is formed. The last steps are deposition of a protective carbonic layer and removal of carbon from the stencil openings by etching. The internal stress control of the finally remaining silicon and carbon layers is decisive for the pattern placement accuracy of the stencil mask. The surface geometry and pattern placement are measured with a LEICA LMS IPRO system at different process steps. The initial bow and warp of the SOI mask-wafer blank is measured. Then, the pattern placement is measured after e-beam writing. After membrane formation the samples are measured a third time followed by a final measurement after carbon layer deposition and etch. These results are to be compared with FE (Fenite Elements) modeling calculations. Compared to previous investigations the effect of wafer warp will be included. Furthermore, LMS IPRO measurements will be done with improved tool accuracy on stencil mask membranes as achieved recently. Thus, the claimed functional dependence between stress and pattern distortion is to be verified experimentally.
Ion Projection Lithography (IPL) is a most promising candidate for next generation IC technology. A critical aspect of IPL is the development of stencil masks with proper stress control. Thus, precise stress measurement of stencil mask membranes is mandatory. The work presented in this paper is based on the well known bulging method. The Silicon lattice contraction by boron doping was investigated experimentally on SOI 150 mm masks with 3 micrometer thick membranes of 126 mm diameter. The measured Si membrane stress vs. boron doping was compared with theoretical models. This comparison shows that a three dimensional model of stress formation is not appropriate and thus the dependence of stress on boron doping concentration better follows linear model.
Hardmask-less stencil mask making requires masks with a high aspect ratio. The bilayer CARL (chemical amplification of resist lines) process was evaluated and optimized with respect of generating irregular resist features below 180 nm in a film thickness of 750 nm. Especially the dry development was detailed investigated using statistical design and analysis of experiment. Processed CARL resist masks are compared with Top Surface Imaging results. Finally, results of a deep silicon etching process using the CARL resist masks are presented.
Distortion control is one of the key issues to solve for IPL stencil mask development. Placement is measured by a LEICA LMS IPRO system. Registration as well as overlay results and the error contributions of the measurement will be presented. The production flow of IPL stencil masks is marked by the fact, that e-beam patterning is done on the bulk wafer, whereas the removal of the bulk silicon and the creation of the free membrane takes place at the end of the process, after silicon trench etching. Therefore, distortions appear at the release of the membrane after bulk silicon etching and oxide removal. At e-beam patterning, the mask wafer blank is pre-stressed by the sum of the stresses of the different layers as bulk silicon, silicon oxide, the silicon of the latter membrane and resist. Additionally, the initial warp and bow of the mask wafer blank have to be considered. The analysis of the finite element modeling compares the placement at e-beam writing to the situation after membrane completion. With this information, the efficiency of a FE-supported software correction before mask patterning can be improved. Measurements of masks with different stress values are to be discussed in order to deduce the optimum stress values for IPL stencil masks.
Two process flows for the fabrication of stencil masks have been developed. The PN Wafer Flow- and the SOI Wafer Flow Process. Membranes and stencil masks out of different 6 inch Si base wafers with 3 micrometers membrane thickness and a membrane diameter between 120 mm and 126 mm were fabricated. The membrane stress depending on the material property and doping level has been determined. First metrology measurements have been carried out.
Ion beam lithography is one of the most promising future lithography technologies. A helium or hydrogen ion beam illuminates a stencil membrane mask and projects the image with 4X reduction to the wafer. The development of stencil masks is considered to be critical for the success of the new technology. Since 1997, within the European Ion Projection Lithography MEDEA (Microelectronic Devices for European Applications) project silicon stencil masks based on a wafer- flow process are developed. They are produced in a conventional wafer line. Six inch SOI (silicon-on-insulator) wafers are patterned with an e-beam wafer writing tool, then trenches are etched by plasma etching. Afterwards, the membrane is etched by wet etch using the SOI-oxide layer as an etch stop. The last step is to add a coating layer, which is sputtered onto the membrane. It protects the mask against ion irradiation damage. For metrology and inspection, methods used for conventional chromium masks as well as new techniques are investigated. Results from placement measurements on the Leica LMS IPRO tool will be presented. Finally, methods for CD measurement, defect inspection, repair and in-situ-cleaning in the stepper will be discussed, including experimental information of first tests.
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