This PDF file contains the front matter associated with SPIE Proceedings Volume 10587, including the Title Page, Copyright information, Table of Contents, Introduction (if any), and Conference Committee listing.

An overview of advances in MOEMS devices and technologies for high quality imaging systems is provided. A particular focus is laid on recent technological further developments possibly opening gateways to unprecedented device and system functionality by e. g.: increase of pixel count towards higher parallel operation, decrease of the mirror pitch in large arrays towards applications like high-performance holography, novel technologies for higher operation bandwidth, increase of aperture size for scanning applications like LIDAR, integration of high reflection coatings for processing of multi Watt laser radiation for marking and engraving, and phased arrays for high speed laser beam steering.

Spacer-assisted pitch multiplication is a patterning technique that is used on many different critical layers for memory and logic devices. Pitch walk can occur when the spacer process, a combination of lithography, deposition and etch processes, produce a repeating, non-uniform grating of space / line CDs. It has been shown that for spacer-assisted double patterning (SADP), where the lithography pitch is doubled, pitch walk can be reduced by controlling the exposure dose such that the uniformity of the final SADP spaces defined by the core resist mandrel (S1) is balanced with the final SADP space defined by the distance between adjacent SADP lines (S2). For higher pitch multiplications, starting with spacer-assisted quadruple patterning (SAQP) reducing systematic pitch walk with exposure dose becomes more complex.

Co-optimization of the lithography and etch processing is expected to be required to achieve the best pitch walk control. Previous work has shown that improving the across wafer CD uniformity of the line patterns after core etch has limited impact on the space CD uniformity after the SADP process, whereas the CD uniformity of the spaces after SAQP did show some dependence. There are additional space populations created by an SAQP process. The variation of these different populations, along with the spacer deposited line populations, is the root cause of the non-uniform grating that results in pitch walk. The complex interactions of the lithography and etch processes’ impact on the CD and profile need to be understood to produce the optimal performance.

Pitch walk is a component of the overall Edge Placement Error (EPE) budget. With current nodes using SAQP for multiple device layers and future nodes expected to continue to implement this patterning technique, minimization of pitch walk variability is an important part of overall patterning optimizations. In this work, we will show how cooptimized exposure dose and etch processes for SAQP patterning can improve pitch walk performance. We will provide a target exposure dose metric for a 32nm pitch SAQP grating. The methodology for achieving the best pitch walk performance by combination of etch process optimization with dose correction will also be shown.

Use of ArFi lithography requires application-specific tuning to maximize patterning process windows. Previous investigations into the effects of light source bandwidth on imaging performance have provided the foundation for this work by identifying significant improvements in Exposure Latitude for reduced sensitivity to dose variations. This study will focus on the increase in image contrast that 200 fm light source E95 bandwidth enables on Self- Aligned Quadruple Patterning (SAQP) and Self-Aligned Double Patterning (SADP) core features. Focus of our investigation will be the understanding of roughness and profile variation through different exposure conditions.

Abstract With ever shrinking feature sizes, the IC industry continues to seek high quality lithography that includes low line edge roughness (LER), high resolution, and straight pattern profiles with solutions to pattern forbidden pitch and hot spots. This paper will discuss a new approach that is proposed to improve these desired characteristics up to the system’s stochastic limit. The nature of LER is stochastic, which can be considered a barrier of patterning resolution. With this barrier, how can engineers take advantage of minimizing stochastic effects to achieve minimum LER and best resolution all while approaching the limitation of intrinsic roughness? In order to understand these effects, a new criterion is proposed that describes the region where variability can occur, called stochastic area thickness (SAT). The SAT of the resist is calculated from optical imaging and resist contrast curve (including acid diffusion effects). This SAT value will be used to develop a second criterion that accounts for effects only seen during the resist developing process, developed stochastic area thickness (DSAT). The DSAT value can be used as an approximation of the actual stochastic effects in the patterning process. Since pattern formation depends on DSAT value, the number of printable die (NPD), or printability, is chosen as DSAT criteria. A variety of lithography conditions with a variety of SAT values were analyzed using this new approach. The results indicate that DSAT correlates well to printability, LER and pattern profile. However, the approaches to minimize DSAT may contradict methods typically used for conventional lithography. Fortunately, for conventional lithography, the DSAT value has a large margin for improvement, and process and material recommendations are proposed.

Linewidth roughness (LWR) remains a difficult challenge for improvement in all resist materials. In this paper, we intend to focus on the impact of key components of LWR by analyzing the Power Spectral Density (PSD) curves which can be obtained using Fractilia’s MetroLER computational software. We will study systematic changes to ArF resist formulations and correlate these changes to the overall PSD curves. In this manner, we can extract LER/LWR 3σ values as well as resist correlation length and the low/high-frequency roughness components. We will also investigate the relationship between PSD and LWR through lithographic/etch processing and demonstrate which components correspond with the largest impact. In order to achieve quality data over low and high frequency ranges we changed our standard metrology setup to capture longer lines. By making systematic changes to the ArF resists, we can determine the key impacts of various controllable resist factors on the PSD. Through systematic analysis, we can deconvolute LWR improvements both after develop and after an etch process.

Line edge roughness (LER) reduction is critical during the patterning process definition and development, as the critical dimension (CD) and pitch scale in advanced semiconductor technology nodes. In this paper, we will focus on a 7nm self-aligned double patterning (SADP) process for use in back end of line (BEOL). Specifically, we will investigate LER from various lithography options and how LER changes through downstream processes, including mandrel etch, spacer deposition, hard mask open, dielectric etch and wet clean. We characterized LER as a function of several mandrel etch parameters such as O2 flow rate, over etch rate percentage and polymer deposition rates. We also characterized LER response to dielectric etch parameters and found that while some etch processes may smooth high frequency LER, there are additional cases where the final etch and wet-clean increased LER and line wiggling. Overall, we observed that lithography is the primary source of LER and we have the opportunity to reduce LER by both design and process optimization. In this paper we focused on characterization of a standard logic cell with varied CD and pitch. We looked through various designs, retargeting as well as both negative tone developer (NTD) and positive tone developer (PTD) resists for the LER reduction. We also analyzed the image log slope (ILS) of each corresponding edge and the process windows of the resist candidates. We concluded that ILS improvement and resist selection are the primary knobs to reduce LER. With optimization, we can achieve LER close to the process assumption targets for 7nm technology node. Further LER reduction techniques are definitely needed in both 7nm and future nodes even with migration from 193nm to EUV lithography.

EUV lithography enables the transition from multiple patterning in DUV back to single patterning in EUV, with the associated cost benefit. While imaging and patterning becomes easier with EUV, cross-platform overlay performance needs to be taken into account.

With quadruple patterning, the matching performance is driven by the platform capabilities, with platform specific fingerprints not contributing to the matching performance as they are similar for each layer. Introducing EUV automatically means we need to compensate for the differences in the platform fingerprints, as they bring a penalty in the DUV-EUV matching budget.

This paper will explain what the main overlay contributors in cross-platform matched machine overlay are and how they can be cancelled or reduced using additional correction measures, with the goal to reach below 2.0 nm cross matched machine overlay.

We demonstrate high volume manufacturing feasibility of 7 nm technology overlay correction requirement. This stateof- the-art overlay control is achieved by (i) overlay sampling optimization and advanced modeling, (ii) alignment and advanced process control optimization, (iii) multiple target overlay optimization, and (iv) heating control. We will also discuss further improvements in overlay control for 7 nm technology node and beyond including computational metrology, extreme ultraviolet and optic tools overlay matching control, high order alignment correction, tool stability improvement, and advanced heating control.

All wafers moving through a microchip nanofabrication process pass through a lithographic apparatus for most, if not all, layers. With a lithographic apparatus providing a massive amount of data per wafer, this paper will outline how physicsbased models can be used to refine UVLS (ultraviolet level sensor) metrology into four unique inputs for use in a deep learning network. Due to the multi-dimensional cross correlation of our deep learning network, we then show that training to a sparse overlay layout with dense inputs results in a hyper dense overly signature. On a testing dataset blind to the training we show that the accuracy of the predictive computational overlay metrology can capture R² up to 0.81 of the signature in overlay Y. As a real-world application, we outline how our predictive computational overlay metrology can then be used to designate which wafer combinations, coming from the TWINSCAN system, should have overlay measured with a YieldStar system for possible use with APC (advanced process control).

Three methods to minimize the impact of alignment mark asymmetry on overlay variation are demonstrated. These methods are measurement based optimal color weighting (OCW), simulation based optimal color weighting, and wafer alignment model mapping (WAMM). Combination of WAMM and OCW methods delivers the highest reduction in overlay variation of 1.3nm (X direction) and 1.2nm (Y direction) as compared to best single color recipe. Simulation based OCW produces a similar reduction in overlay variation as compared to measurement based OCW, and simulation based OCW has the advantage that the scanner alignment recipe with optimize weights can be determined before the mark asymmetry excursion has occurred. Finally, WAMM is capable of reducing the contribution of mark asymmetry on overlay by using a more optimal high order wafer alignment recipe. Capabilities of WAMM can also be combined with OCW solutions.

Manufacturing embedded DRAM deep trench capacitors can involve etching very deep holes into silicon wafers¹. Due to various design constraints, these holes may not be uniformly distributed across the wafer surface. Some wafer processing steps for these trenches results in stress effects which can distort the silicon wafer in a manner that creates localized alignment issues between the trenches and the structures built above them on the wafer.

In this paper, we describe a method to model these localized silicon distortions for complex layouts involving billions of deep trench structures. We describe wafer metrology techniques and data which have been used to verify the stress distortion model accuracy. We also provide a description of how this kind of model can be used to manipulate the polygons in the mask tape out flow to compensate for predicted localized misalignments between design shapes from a deep trench mask and subsequent masks.

All chipmakers understand that variability is the enemy of any process and that defectivity reduction is essential to improving yield which translates to profit. Aggressive process window and yield specifications put tight requirements on the DUV light source which will impact scanner imaging performance. Accurate identification of defectivity caused by on wafer hotspots along with the impact on process windows can be accomplished using existing industry capability. ASML’s Brion Lithography Manufacturing Checker (LMC) can be employed using existing models to perform hotspot analysis and verify process window impact for current and future 193 nm nodes. In this presentation, we review a methodology to understand the effect bandwidth variation has on hotspot variability and defect variation on specific customer designs. Initial studies are based on a large number of customer specific 90 nm pitch layouts where bandwidth variability is investigated for its impact on hotspot variability. Defect density maps are generated from the baseline process with additional maps generated at various bandwidth ranges. This methodology has been applied to Cymer’s DynaPulse and new DynaPulse2 bandwidth control technologies demonstrating the impact that bandwidth variation can influence process defectivity levels.

Within the current paper, we will concentrate on the well-known CDC technique from Carl Zeiss to improve the CD distribution of the wafer by improving the reticle CDU and its impact on hotspots and Litho process window. The CDC technique uses an ultra-short pulse laser technology, which generates a micro-level Shade-In-Element (also known as "Pixels") into the mask quartz bulk material. These scatter centers are able to selectively attenuate certain areas of the reticle in higher resolution compared to other methods and thus improve the CD uniformity.

In a first section, we compare the CDC technique with scanner dose correction schemes. It becomes obvious, that the CDC technique has unique advantages with respect to spatial resolution and intra-field flexibility over scanner correction schemes, however, due to the scanner flexibility across wafer both methods are rather complementary than competing. In a second section we show that a reference feature based correction scheme can be used to improve the CDU of a full chip with multiple different features that have different MEEF and dose sensitivities. In detail we will discuss the impact of forward scattering light originated by the CDC pixels on the illumination source and the related proximity signature. We will show that the impact on proximity is small compared to the CDU benefit of the CDC technique.

Finally we show to which extend the reduced variability across reticle will result in a better common electrical process window of a whole chip design on the whole reticle field on wafer. Finally we will discuss electrical verification results between masks with purposely made bad CDU that got repaired by the CDC technique versus inherently good “golden” masks on a complex logic device. No yield difference is observed between the repaired bad masks and the masks with good CDU.

Inverse lithography is increasingly being used as a viable OPC solution to maximize process window (PW), improve CD uniformity (CDU) and minimize the mask error factor (MEF), especially for memory devices. The device yield is typically limited by the process window of a few critical layers, and the Via layer is identified as one of the process window limiters for advanced 3D-NAND devices. To maximize the on-chip yield, ASML has developed advanced image based Mask-3D (M3D) inverse technology that can optimize freeform mask shapes and enhance design printability throughout the mask optimization flow. Mask rule checks (MRC) and side-lobe printing are optimized simultaneously to deliver the maximum process window.

The advanced image based M3D inverse lithography technology (ILT) is used to perform full chip mask correction on the Via layer of a 3D-NAND device. 3D NAND devices contain highly repetitive cell and page buffer patterns. To ensure the full chip device performance, the consistency of the mask correction is important. Our strategy is to use the computationally intensive mask optimization solution from the new advanced image based M3D inverse technology to generate a freeform mask which gives the best lithography performance. We then use Tachyon’s Pattern Recognition and Optimization (PRO) engine to propagate the freeform mask solution of the repetitive patterns to the full chip. The periphery of the chip is optimized using conventional OPC methods. The simulation results from the advanced image based M3D inverse technology are compared against the baseline flow, which uses a standard inverse solution. The simulation results from both the flows are further validated on wafer. Significant improvement in overlapping process window (OPW) and CD uniformity is observed using the new advanced inverse technology. The simulation data shows a 32% improvement in depth of focus (DOF), a 5% improvement in the image log slope (ILS) and a 25% reduction in best focus shift (BFS) range. The improvement has also been verified at the wafer-level.

Deep neural networks (DNN) have been widely used in many applications in the past few years. Their capabilities to mimic high-dimensional complex systems make them also attractive for the area of semiconductor engineering, including lithographic mask design. Recent progress of mask writing technologies, including emergent techniques such as multi-beam raster scan mask writers, has made it possible to produce curvilinear masks with essentially “any” shapes. The increased granularity of mask shapes brings enormous advantages and challenges to resolution enhancement techniques (RET) such as optical proximity correction (OPC), Inverse lithography technologies (ILT), and other advanced mask optimization tools. Attempts of replacing the conventional segment based OPC by the ILT and other advanced solutions for full chip mask tapeout have been around for over a decade. Extremely slow mask data total-turnaround time is one of the major blocks. Therefore, its applications have been limited to small clip based applications such as for scanner source optimization, mask optimization only used for hotspot fixing and hierarchical memory designs. In this paper we present a new technique to apply DNN in our newly developed GPU-accelerated mask optimization platform, which reduces the runtime significantly without sacrificing the accuracy and convergence. This new tool combines deep learning, GPU computing platform and advanced optimization algorithms, and provides a fast and accurate solution for mask optimization in the sub-10nm tech nodes.

An approach of solving the inverse lithography problem as a nonlinear, constrained minimization problem over a domain of mask pixels was suggested in the paper by Yu. Granik "Fast pixel-based mask optimization for inverse lithography'' in 2006.

This idea was advanced to account for pinching and bridging print contour constraints in the paper "Controlling Bridging and Pinching with Pixel-based Mask for Inverse Lithograph'' by S. Kobelkov and others in 2015.

The present paper extends this approach further for solving the enclosure print image constraints, getting maximum common depth of focus, and obtaining uniform PV-bands.

Namely, we suggest several objective functions that express penalty for constraint violations. Their minimization with gradient descent methods is considered. A number of applications have been tested with ILTbased pxOPC tool for DUV metal, contacts, and EUV metal layouts; results are discussed showing benefits of each approach.

The resist effect may have a significant impact on source mask optimization (SMO), because the CD change in response to dose, defocus and mask size variations can be substantially modified by the resist effect. In this paper, we elaborate on how the resist effect, represented by compact resist models, changes the cost function of SMO and affects the optimized source shapes and the corresponding lithographic performance. Based on the results, we present the guidelines of using compact resist models in SMO, especially for the case of the negative tone development (NTD) process.

Traditionally, optical proximity correction (OPC) on cell array patterns in memory layout uses simple bias rules to correct hierarchically-placed features, but requires intensive, rigorous lithographic simulations to maximize the wafer process latitude. This process requires time-consuming procedures to be performed on the full chip (excluding the cell arrays) to handle unique cell features and layout placements before (and even sometimes after) OPC. The time required limits productivity for both mask tapeouts and the wafer process development. In this paper, a new cell array OPC flow is introduced that reduces turnaround-time for mask tapeouts from days to hours, while maintaining acceptable OPC quality and the perfect geometric consistency on the OPC output that is critical for memory manufacturing. The flow comprises an effective sub-resolution assist features (SRAFs) insertion and OPC for both the cell array and the peripheral pattern areas. Both simulation and experimental results from actual wafer verification are discussed.

Sub-resolution assist feature (SRAF) insertion techniques have been effectively used for a long time now to increase process latitude in the lithography patterning process. Rule-based SRAF and model-based SRAF are complementary solutions, and each has its own benefits, depending on the objectives of applications and the criticality of the impact on manufacturing yield, efficiency, and productivity. Rule-based SRAF provides superior geometric output consistency and faster runtime performance, but the associated recipe development time can be of concern. Model-based SRAF provides better coverage for more complicated pattern structures in terms of shapes and sizes, with considerably less time required for recipe development, although consistency and performance may be impacted. In this paper, we introduce a new model-assisted template extraction (MATE) SRAF solution, which employs decision tree learning in a model-based solution to provide the benefits of both rule-based and model-based SRAF insertion approaches. The MATE solution is designed to automate the creation of rules/templates for SRAF insertion, and is based on the SRAF placement predicted by model-based solutions. The MATE SRAF recipe provides optimum lithographic quality in relation to various manufacturing aspects in a very short time, compared to traditional methods of rule optimization. Experiments were done using memory device pattern layouts to compare the MATE solution to existing model-based SRAF and pixelated SRAF approaches, based on lithographic process window quality, runtime performance, and geometric output consistency.

Despite the large difficulties involved in extending 193i multiple patterning and the slow ramp of EUV lithography to full manufacturing readiness, the pace of development for new technology node variations has been accelerating. Multiple new variations of new and existing technology nodes have been introduced for a range of device applications; each variation with at least a few new process integration methods, layout constructs and/or design rules. This had led to a strong increase in the demand for predictive technology tools which can be used to quickly guide important patterning and design co-optimization decisions.

In this paper, we introduce a novel hybrid predictive patterning method combining two patterning technologies which have each individually been widely used for process tuning, mask correction and process-design cooptimization. These technologies are rigorous lithography simulation and inverse lithography technology (ILT). Rigorous lithography simulation has been extensively used for process development/tuning, lithography tool user setup, photoresist hot-spot detection, photoresist-etch interaction analysis, lithography-TCAD interactions/sensitivities, source optimization and basic lithography design rule exploration. ILT has been extensively used in a range of lithographic areas including logic hot-spot fixing, memory layout correction, dense memory cell optimization, assist feature (AF) optimization, source optimization, complex patterning design rules and design-technology co-optimization (DTCO). The combined optimization capability of these two technologies will therefore have a wide range of useful applications. We investigate the benefits of the new functionality for a few of these advanced applications including correction for photoresist top loss and resist scumming hotspots.

Various computational approaches from rule-based to model-based methods exist to place Sub-Resolution Assist Features (SRAF) in order to increase process window for lithography. Each method has its advantages and drawbacks, and typically requires the user to make a trade-off between time of development, accuracy, consistency and cycle time.

Rule-based methods, used since the 90 nm node, require long development time and struggle to achieve good process window performance for complex patterns. Heuristically driven, their development is often iterative and involves significant engineering time from multiple disciplines (Litho, OPC and DTCO).

Model-based approaches have been widely adopted since the 20 nm node. While the development of model-driven placement methods is relatively straightforward, they often become computationally expensive when high accuracy is required. Furthermore these methods tend to yield less consistent SRAFs due to the nature of the approach: they rely on a model which is sensitive to the pattern placement on the native simulation grid, and can be impacted by such related grid dependency effects. Those undesirable effects tend to become stronger when more iterations or complexity are needed in the algorithm to achieve required accuracy.

ASML Brion has developed a new SRAF placement technique on the Tachyon platform that is assisted by machine learning and significantly improves the accuracy of full chip SRAF placement while keeping consistency and runtime under control. A Deep Convolutional Neural Network (DCNN) is trained using the target wafer layout and corresponding Continuous Transmission Mask (CTM) images. These CTM images have been fully optimized using the Tachyon inverse mask optimization engine. The neural network generated SRAF guidance map is then used to place SRAF on full-chip. This is different from our existing full-chip MB-SRAF approach which utilizes a SRAF guidance map (SGM) of mask sensitivity to improve the contrast of optical image at the target pattern edges.

In this paper, we demonstrate that machine learning assisted SRAF placement can achieve a superior process window compared to the SGM model-based SRAF method, while keeping the full-chip runtime affordable, and maintain consistency of SRAF placement . We describe the current status of this machine learning assisted SRAF technique and demonstrate its application to full chip mask synthesis and discuss how it can extend the computational lithography roadmap.

In advanced nodes, the extension of DUV lithography deep into the sub-wavelength dimensions has led to exploration of many new Resolution Enhancement Techniques (RET). Generally speaking, these RET have enabled higher resolution capabilities using the same exposure wavelength, but at the cost of increasingly complex mask optimization process. One such technique applied to perform Optical Proximity Correction (OPC) is called Inverse Lithography Technique (ILT). It promises the best possible theoretical mask design by solving the inverse problem, where the optical transform from mask to wafer image is solved in reverse using a rigorous mathematical approach [1]. Although the benefits and potentials of ILT in producing a single exposure mask are well documented [2], its implementation in multiple patterning OPC (MP-OPC) is less explored. In this paper, an ILT mask optimization is applied on a metal layer, consisting of 3 exposures in a litho-etch x 3 (LELELE) process flow. It demonstrates the application of both multi-exposure and etch awareness within the ILT mask correction scheme. This is accomplished by including inter-layer constraints for the resist and the post-etch contours in the objective function of the ILT optimization. The ability to reduce potential interexposure failure modes as well as the associated increase in computational resources will be assessed. Additionally, the results will be compared against a conventional model-based OPC with similar multi-exposure and etch awareness.

As semiconductor product development based on shrinkage continues, the accuracy and difficulty required for the model based optical proximity correction (MBOPC) is increasing. OPC simulation time, which is the most timeconsuming part of MBOPC, is rapidly increasing due to high pattern density in a layout and complex OPC model.

To reduce OPC simulation time, we attempt to apply graphic processing unit (GPU) to MBOPC because OPC process is good to be programmed in parallel. We address some issues that may typically happen during GPU-based OPC simulation in multi thread system, such as “out of memory” and “GPU idle time”. To overcome these problems, we propose a thread scheduling method, which manages OPC jobs in multiple threads in such a way that simulations jobs from multiple threads are alternatively executed on GPU while correction jobs are executed at the same time in each CPU cores. It was observed that the amount of GPU peak memory usage decreases by up to 35%, and MBOPC runtime also decreases by 4%. In cases where out of memory issues occur in a multi-threaded environment, the thread scheduler was used to improve MBOPC runtime up to 23%.

As the technology node for the semiconductor manufacturing approaches advanced nodes, the scattering-bars (SBs) are more crucial than ever to ensure a good on-wafer printability of the line space pattern and hole pattern. The main pattern with small pitches requires a very narrow PV (process variation) band. A delicate SB addition scheme is thus needed to maintain a sufficient PW (process window) for the semi-iso- and iso-patterns. In general, the wider, longer, and closer to main feature SBs will be more effective in enhancing the printability; on the other hand, they are also more likely to be printed on the wafer; resulting in undesired defects transferable to subsequent processes. In this work, we have developed a model based approach for the scattering-bar printing avoidance (SPA). A specially designed optical model was tuned based on a broad range of test patterns which contain a variation of CDs and SB placements showing printing and non-printing scattering bars. A printing threshold is then obtained to check the extra-printings of SBs. The accuracy of this threshold is verified by pre-designed test patterns. The printing threshold associated with our novel SPA model allows us to set up a proper SB rule.

As the computational requirements for post tape out (PTO) flows increase at the 7nm and below technology nodes, there is a need to increase the scalability of the computational tools in order to reduce the turn-around time (TAT) of the flows. Utilization of design hierarchy has been one proven method to provide sufficient partitioning to enable PTO processing. However, as the data is processed through the PTO flow, its effective hierarchy is reduced. The reduction is necessary to achieve the desired accuracy. Also, the sequential nature of the PTO flow is inherently non-scalable. To address these limitations, we are proposing a quasi-hierarchical solution that combines multiple levels of parallelism to increase the scalability of the entire PTO flow. In this paper, we describe the system and present experimental results demonstrating the runtime reduction through scalable processing with thousands of computational cores.

Biopolymers represent natural, renewable and abundant materials. Their use is steadily growing in various areas (food, health, building …) but, in lithography, despite some works, resists, solvents and developers are still oil-based and hazardous chemicals. In this work, we replaced synthetic resist by chitosan, a natural, abundant and hydrophilic polysaccharide. High resolution sub-micron patterns were obtained through chitosan films as water developable, chemically unmodified, positive tone mask resist for an eco-friendly electron beam and deep-UV (193 nm) lithography process. Sub-micron patterns were also successfully obtained using a 248 nm photomasker thanks to the addition of biosourced photoactivator, riboflavin. Patterns were then transferred by plasma etching into silica even for high resolution patterns.

From the first digital cameras which appeared during the 70s to cameras of current smartphones, image sensors have undergone significant technological development in the last decades. The development of CMOS image sensor technologies in the 90s has been the main driver of the recent progresses. The main component of an image sensor is the pixel. A pixel contains a photodiode connected to transistors but only the photodiode area is light sensitive. This results in a significant loss of efficiency. To solve this issue, microlenses are used to focus the incident light on the photodiode. A microlens array is made out of a transparent material and has a spherical cap shape. To obtain this spherical shape, a lithography process is performed to generate resist blocks which are then annealed above their glass transition temperature (reflow).

Even if the dimensions to consider are higher than in advanced IC nodes, microlenses are sensitive to process variability during lithography and reflow. A good control of the microlens dimensions is key to optimize the process and thus the performance of the final product.

The purpose of this paper is to apply SEM contour metrology [1, 2, 3, 4] to microlenses in order to develop a relevant monitoring methodology and to propose new metrics to engineers to evaluate their process or optimize the design of the microlens arrays.

‘Double’ Displacement Talbot Lithography (D2TL) is proposed as a new, high-throughput and rapid tool that allows the fabrication of complex periodic nano- to micron patterns over a large area (up to 100 200 mm). This method is a combination of conventional Displacement Talbot Lithography (DTL) [1] and a planar displacement to make more complex shapes. The more straight-forward DTL technique utilizes the periodic diffraction pattern on all space axes that results when a periodic mask is illuminated by a planar wave (Talbot effect); by displacing the wafer along the axis of illumination over integer spatial periods, called the Talbot length, the low depth of field is overcome. In D2TL, by additionally moving the wafer perpendicular to the axis of illumination, the range and complexity of features possible across whole wafers is dramatically extended. Furthermore, a single periodic mask can be used to create a large number of different patterns by using different lateral displacements. In order to demonstrate the capability of this technique, a number of proof-of-principle experiments have been performed using a hexagonal mask with a 1.5 micron pitch with a positive i-line resist on silicon wafers. Firstly, dual exposures before and after sub-micron, nm-precision, translations show the transition between coincident, merged and isolated features. Secondly, circular displacements of differing amplitudes were applied during single exposures, which led to a large variety of shapes being obtained: positive or negative honeycomb, large dot or large holes, rings and periodic cancelation of dot site with a change of pitch. These results compare well with simulations created using MATLAB that calculate the integrated intensity distribution for each lateral position in the photoresist. Importantly, the simulations take into account weaker, secondary features in the intensity map that result from unwanted constructive interference. The modelling allows greater insights into these secondary patterns, helping to diminish their impact through tuning the filling factor and pitch of the hexagonal mask. The complexity of patterns that can be produced using this technique depends on the minimum feature size for a given periodicity and the relative intensity of any unwanted secondary features. Simulations of the intensity maps coupled with the development model of high-contrast, i-line resists show a strong influence on whether an amplitude or phase mask is used, with a strong non-linear dependence on pitch and filling factor of the mask. Specific optimum masks can be identified that offer the greatest opportunity for exploiting this new technique. In summary, D2TL offers the possibility to create a multitude of patterns from a single mask by simply controlling the lateral displacement during or between successive exposures. Successful implementation of this technique requires an in-depth understanding of the DTL process and simulation tools to correctly account for proximity effects. [1] H H Solak, C Dais, and F Clube, Displacement Talbot lithography: a new method for high-resolution patterning of large areas, Opt. Express 19, 10686-10691 (2011).

We present and discuss Talbot mask-aligner lithography, relying on a continuous wave laser emitting at 193nm for the illumination. In this source, a diode laser at 772nm is amplified by a tapered amplifier in master-oscillator power-amplifier configuration and frequency-quadrupled in two subsequent enhancement cavities using lithium triborate and potassium fluoro-beryllo-borate nonlinear crystals to generate the emission at 193 nm. The high coherence and brilliance of such an illumination source is predestined for plane wave mask-aligner illumination, crucial in particular for high-resolution lithographic techniques such as Talbot lithography and phase-shift masks. Talbot lithography takes advantage of the diffraction effect to image periodic mask features via self-replication in multiples of the Talbot distance behind the photomask when exposed by a plane wave. By placing a photoresistcoated wafer in one of the Talbot planes, the mask pattern is replicated in the resist. Periodic patterns with diverse shapes are required for wire grid polarizers, diffraction gratings, and hole arrays in photonic applications as well as for filters and membranes. Using an amplitude mask with periodic structures, we demonstrate here with such a technique sub-micron feature sizes for various designs at a proximity gap of 20 µm.

In order to meet the industry’s increasingly demanding requirements, especially in the area of improving pattern edge placement error for multiple patterning processes, we have developed the leading edge NSR-S635E ArF immersion scanner. The NSR-S635E delivers marked enhancements in scanner performance compared to the previous generation system, and provides expanded alignment capacity with a groundbreaking system called the inline Alignment Station (iAS) [1]. In this paper, we introduce the details of the NSR-S635E, including iAS, and demonstrate their capabilities for solving production challenges now and in the future.

DUV ArF immersion lithography requires patterning budget improvements in the range of 1/10 nm especially for interconnect layers for advanced process nodes. As every angstrom counts, the Cymer XLR 860ix light source has been developed to deliver the performance required for multiple patterning processes across all sectors: DRAM, 3D NAND, and logic. This paper will describe how imaging margins can be increased by optimizing light source bandwidth settings. Advancements include new hardware and software that enable industry leading bandwidth performance and control. In addition, on-wafer measurements were collected showing the progressive improvements gained with lowering bandwidth on an existing mask. As system availability is a key enabler for chipmakers, the introduction of this new DUV light source includes improvements that continue to improve productivity by increasing service intervals by >30% while also providing sustainability enhancements.

High efficiency coupling of the array of UV light diode light source could be able to replace the traditional mercury light source, while mercury light source requires a large amount of electricity, condenser optics and volume, with hazard environmental issue. It is an urgent need for further requirement of light source for lithography. Although array UVLED could be a replacement of light sources of lithography, there are some existent optical parameters that not fit for optical coupling, such as large divergent cone angle of single chip and half divergent angle of array, which are weak the possibility of application in lithography. Before the broadly accepted by lithography, those shortages have to be overcome. Some techniques, such as designing small divergent cone angle of single chip, or eliminating divergent angle have suggested by fly eye and other methods, yet all of those methods, only improve the coupling efficiency and uniformity of emitted surface in some limited extent. The project is to develop a high coupling efficiency of the optical system used in the array of UV light diodes, which can make the high coupling efficiency, despite UVLED has a small size and large divergent angle. The optical design of illumination has carried out for array UVLED, an illumination optics has designed based on Koehler type illumination, and it has shown reducing the divergent angle to increase in coupling efficiency between the Array UVLED to the mask of lithography. The uniformity of average power has shown excellently fitted for high quality lithography in direct exposure or lens exposure.

Multiple patterning ArF immersion lithography has been expected as the promising technology to meet tighter process control requirements. The most important features for the next generation light sources are improvement of chip yield, enhancement of productivity and reduction of operational costs for chipmakers [1][2]. One of key performance for light source is E95 bandwidth, which has become more important parameter for enhancing process margin and improving device productivity. A faster actuator to move a lens improves E95 bandwidth stability [3]. This technology enables 3σ of E95 bandwidth field average to be under 10 fm. This contributes to more precise CD control and improves device yield. Latest LNM enables E95 bandwidth to lower from the standard 300 fm to 200 fm [4]. The large shrinkage for E95 bandwidth is achieved by introducing the ingenious design in LNM. High purity E95 bandwidth improves imaging contrast and therefore increases exposure latitude. A new control algorithm enables E95 bandwidth to vary up to 450 fm, leveraging the movable lens. The combination of the new LNM, the movable lens and the new bandwidth control algorithm enables E95 bandwidth to control between 200 fm and 450 fm [5]. The tunable E95 bandwidth technology can improve process productivity for chip makers by compensating not only machine to machine difference of imaging contrast but also difference of imaging contrast between different generation scanners. The tunable E95 bandwidth technology has no influence on key laser performance indicator, dose stability, wavelength stability, E95 bandwidth stability, etc. On the other hand, to reduce downtime and operational costs for chipmakers, the lifetime of consumable modules such as a chamber and a line narrowing module (LNM) is needed to be extended. New electrodes with chamber enables chamber lifetime to extend from 60 billion pulses (Bpls) to 70 Bpls. Furthermore, new optical design in LNM enables the lifetime to extend from 60 Bpls to 110 Bpls. A new ArF excimer laser, GT65A, maximizes device yield, process productivity and minimizes the operational costs for chipmakers.

Absorption-induced lens heating within optical elements can diminish the achievable resolution of the lithographic process in semiconductor wafer steppers, as the distortion of the transmitted wavefront leads to deteriorations of the imaging performance. In reverse, sensitive monitoring of thermally induced wavefront distortions also establishes a procedure for fast and precise absorption measurements, since the extent of deformation is directly proportional to the absorption loss. In this paper a parallelized photo-thermal absorption measurement system based upon a Hartmann-Shack wavefront sensor with extreme sensitivity is presented, providing quantitative absorptance data of optical materials with sub-ppm resolution. Caused by the temperature dependence of the refractive index as well as thermal expansion, the initially plane wavefront of a probe beam is distorted into a convex or concave lens, depending on sign and magnitude of index change and expansion. Wavefront deformations as low as 50pm (rms) can be registered. Moreover, due to the spatial resolution of the employed wavefront sensor, the technique is insensitive to misalignments, allowing for a rapid and reliable assessment of material quality. Absolute calibration of the absorption data is achieved by comparison with a thermal calculation. The method accomplishes not only to measure absorptances of plane optical elements, but also wavefront deformations and focal shifts in lenses as well as in complex optical systems. Thus, it is employed already at many places in the semiconductor industry for quality assurance of test optics and components. Along with a description of the technique we present results from absorption measurements on coated and uncoated optics as well as mirrors for 193nm and 248nm. Extensions to EUV optics are discussed.

The light source continues to play an important role in the evolution of semiconductor lithography - helping chip manufacturers to usher in their next generation nodes. Over the years, Gigaphoton has introduced innovative solutions to meet the various demands of the industry, including Injection Lock technology, active bandwidth control, and green technologies for conserving gas and electricity. Today, the needs of chip manufacturer have grown to become highly diverse and dynamic, because the set of challenges faced by each manufacturer is equally diverse and dynamic. This makes developing software solutions very challenging - as they must address a very broad scope of needs. At the same time, it is becoming increasingly important to gain a much deeper understanding of all aspects of how and to what level the light source is actively affecting each chip manufacturer’s wafer output - both in terms of yield and cost - for solutions and technologies to be effective and meaningful. However, there are many challenges to achieving this.

Conventionally, lithography technology has contributed to the miniaturization of semiconductors by improving resolutions achieved though making wavelength shorter and shorter. However, with the advent of immersion lithography and multiple patterning technologies, the trend of shorter wavelength has slowed down. Instead, immersion lithography technology is playing a major role to support mass production. In the past years, lithography units have achieved further evolution enabling the contrast to be further improved by mitigating optical aberration gap. In line with this, a parameter called E95 which is for Monochromaticity for light sources has been mitigated, which made it possible to further reduce the spectrum width.Assuming that optical setting parameters NA and σ are set for the same value in a legacy lithography unit and a latest model lithography unit, there should be differences in parameters such as Iso-Dense Bias which is sensitive to contrast, due to optical differences and the difference in contrast caused by the optical differences. For mass production sites equipped with various immersion lithography units keeping up with the times, we have studied the feasibility to compensate the CD bias differences caused by the differences in NA and σ settings, by handling the light source E95% as a variable number. We have also derived the scopes (coverages) necessary for E95% to compensate gaps between existing units or recipes, and presented optical challenges with the E95% set for what we derived.

With shrinking nodes, as the layout patterns are becoming more and more complicated, OPC accuracy and performance is becoming increasingly challenging. While we are trying to perfect our OPC script to have a clean output without weak points, in a real urgent tape-out scenario, often there will be weak points and we cannot afford the cost to run the OPC again with an updated OPC recipe. Naturally the post OPC repair becomes the only cost-effective choice. The paper studies and compares a few methods for the post OPC weak-points repair: the manual OPC repair flow and traditional repair flow based on the DRC commands. Here, we introduce a novel method based on the eqDRC commands, which are widely used in the design house but have never been used in the post OPC flow. We discuss how to apply the eqDRC into the post OPC repairs and demonstrate its advantages over the traditional methods.

Key sustainability opportunities have been executed in support of corporate initiatives to reduce the environmental footprint and decrease the running cost of DUV light sources. Previously, substantial neon savings were demonstrated over several years through optimized gas management technologies. Beyond this work, Cymer is developing the XLGR 100, a self-contained neon recycling system, to enable minimal gas consumption. The high efficiency results of the XLGR 100 in a production factory are validated in this paper.

Cymer has also developed new light source modules with 33% longer life in an effort to reduce raw and associated resource consumption. In addition, a progress report is included regarding the improvements developed to reduce light source energy consumption.

Smartphone require limit space for image system, current lens, used in smartphones are refractive type, the effective focal length is limited the thickness of phone physical size. Other, such as optro-electronics sensing chips, proximity optical sensors, and UV indexer chips are integrated into smart phone with limit space. Due to the requirement of multiple lens in smartphone, proximity optical sensors, UV indexer and other optro-electronics sensing chips in a limited space of CPU board in future smart phone, optro-electronics 3D IC’s integrated with optical lens or components may be a key technology for 3 C products. A design for reflective lens is fitted to CMOS, proximity optical sensors, UV indexer and other optro-electronics sensing chips based on 3-D IC. The reflective lens can be threes times of effective focal lens, and be able to resolve small object. The system will be assembled and integrated in one 3-D IC more easily.

Developing a new lithographic process routinely involves usage of lithographic toolsets and much engineering time to perform data analysis. Process transfers between fabs occur quite often. One of the key assumptions made is that lithographic settings are equivalent from one fab to another and that the transfer is fluid. In some cases, that is far from the truth. Differences in tools can change the proximity effect seen in low k1 imaging processes. If you use model based optical proximity correction (MBOPC), then a model built in one fab will not work under the same conditions at another fab. This results in many wafers being patterned to try and match a baseline response. Even if matching is achieved, there is no guarantee that optimal lithographic responses are met. In this paper, we discuss the approach used to transfer and develop new lithographic processes and define MBOPC builds for the new lithographic process in Fab B which was transferred from a similar lithographic process in Fab A. By using PROLITH^TM simulations to match OPC models for each level, minimal downtime in wafer processing was observed. Source Mask Optimization (SMO) was also used to optimize lithographic processes using novel inverse lithography techniques (ILT) to simultaneously optimize mask bias, depth of focus (DOF), exposure latitude (EL) and mask error enhancement factor (MEEF) for critical designs for each level.

In the mask manufacturing process, the thickness and sidewall angle of mask are usually determined under the condition of vertical incidence. In fact, the incident angle of light on the mask plane is oblique, especially for the freeform source in source mask optimization (SMO). At this time, the thickness and sidewall angle of mask given by previous methods will not be optimal. This paper presents a method of optimizing mask parameters, which makes the transmittance and phase shift are more optimal for lithography process. In this paper, the influence of variations on mask parameters on lithography process is evaluated by the process window. And the process window corresponding to the optimal mask structure given by our method is larger than that of the original mask structure. The conclusion that the previous mask parameters are not the optimal for lithography process is demonstrated by the simulation results.

With the extension of lithography simulations from low-NA to hyper-NA for immersion lithography and from scalar optics to vector optics including the polarization effect at source, mask, lens and resist film stack, inverse lithography technology (ILT) schemes based on the scalar imaging models which provide sufficient accuracy for NA less than 0.4, cannot track the whole process of polarized light propagation through the optical components of the lithography system rendering their impotence in hyper-NA immersion systems. In this paper, we address the mask synthesis problem by developing a optimization framework based on the vector imaging model fully describing the vector nature of electromagnetic fields in the aerial imaging formation and the stratified media model for the resist image, which is further reduced to a variational level-set based time-dependent model combining an internal energy term forcing the level set function close to a signed distance function and an extra energy term that drives the zero level set toward desired mask features minimizing the pattern difference between the printed wafer and the desired pattern, thereby optimizing the mask layout without the costly re- initialization procedure and ensuring the stability of the evolution of level surfaces. Represented by a partial differential equation, the time-dependent model is readily solved by finite difference schemes. Acceleration of over 30 times of the optimization procedure is achieved by computing convolution operations in the frequency domain with fast fourier transfrom (FFT) and the repeated usage of data, together with a 50% convergency performance improvement by means of applying Polak-Ribi`ere-Polyak (PRP) conjugate gradient (CG) to updating the normal velocity of the level-set function, which are merited by the experimental results.

Due to the lithography demanding high performance in projection of semiconductor mask to wafer, the lens has to be almost free in spherical and coma aberration, thus, in situ optical testing for diagnosis of lens performance has to be established to verify the performance and to provide the suggesting for further improvement of the lens, before the lens has been build and integrated with light source. The measurement of modulation transfer function of critical dimension (CD) is main performance parameter to evaluate the line width of semiconductor platform fabricating ability for the smallest line width of producing tiny integrated circuits. Although the modulation transfer function (MTF) has been popularly used to evaluation the optical system, but in lithography, the contrast of each line-pair is in one dimension or two dimensions, analytically, while the lens stand along in the test bench integrated with the light source coherent or near coherent for the small dimension near the optical diffraction limit, the MTF is not only contributed by the lens, also by illumination of platform. In the study, the partial coherence modulation transfer function (PCMTF) for testing a lithography lens is suggested by measuring MTF in the high spatial frequency of in situ lithography lens, blended with the illumination of partial and in coherent light source. PCMTF can be one of measurement to evaluate the imperfect lens of lithography lens for further improvement in lens performance.

This paper reviews the technical solutions for reduction optical photolithography systems based on the principle of obtaining a scaled-down object image. Dioptric reduction system design trends are discussed and applied technical solutions for building such systems are proposed. Genuine optical systems are offered which comply with the requirements mentioned above.

We introduce a novel industrial grade 193nm continuous-wave laser light source for proximity mask-aligner lithography. A diode seed laser in master-oscillator power-amplification configuration is frequency-quadrupled using lithiumtriborate and potassium-uoro-beryllo-borate non-linear crystals. The large coherence-length of this monomodal laser is controlled by static and rotating shaped random diffusers. Beam shaping with imaging and non-imaging homogenizers realized with diffractive and refractive micro-optical elements is compared in simulation and measurement. We demonstrate resolution patterns offering resolutions <2 µm printed with proximity gaps of 20 µm.

Scanner induced pattern shifts between layers are a large contributor to DRAM Bitline to Active overlay. One of the main root causes for this Pattern Shift non-Uniformity are lens aberrations. Currently measuring the Bitline to Active overlay requires a decap CDSEM method¹. In this paper, an in-resist pattern shift uniformity metrology method is proposed which quantifies the main DRAM Bitline to Active overlay without the necessity to decap. We have designed a high transmission reticle (≥ 60%) to measure the pattern shift non-uniformity between two dense gratings under the rotation angle of the Active layer in both cold and hot lens states. Each module on the reticle contains product-like features and a variety of metrology targets, i.e. alignment and overlay, such that the product-to-product and the productto- metrology pattern shift fingerprints can be measured. OPC is applied to enlarge the overlapping process windows of the metrology targets with respect to the product-like features.

Inverse lithography is most commonly utilized to guide optimizing RET (Resolution Enhancement Technology) solution such as SRAF (Sub-resolution Assist Feature) placement and OPC (Optical Proximity Correction) edge dissection and fragmentation. Inverse lithography recipe often features an array of user-controlled parameters, which allow refined tuning of inverse solution maximizing for various common objectives such as common DOF, NILS, and pvband (process variability band). In practice, some test case shows that the inverse lithography engine can be perturbed to produce novel solution maximizing other unconventional objectives such as OPC solution’s mask-friendliness, OPC convergence at extreme dense-to-iso transition, and multi-structure common focus range. However, the parameter tuning process can be time-consuming and requires expert knowledge of the tool. Also, parameters correlation to those objectives is often highly non-linear. All these reasons make inverse lithography recipe parameter tuning for unconventional objective a non-trivial task. Genetic Algorithm (GA) has been demonstrated to be effective at solving non-trivial optimization tasks such as SRAF rule optimization [1], OPC recipe optimization [2,3] and source mask optimization [4-6], and. Here we propose to use modified GA based engine for inverse lithography recipe optimization. We will show experimental results and discuss the benefits and challenges. We will demonstrate with three real test cases that this flow has a reasonable TAT and improved inverse lithography solutions.

Patterning defects are considered primary killers for device yield and effective defect reduction is critical for semiconductor manufacturing. In the current work, a new positive tone development method is discussed to reduce defects for the 193 nm immersion lithography process. Photoresist develop processing is optimized via tuning of different process related parameters for complete coverage of the developer solution. Meanwhile, splash during development was minimized to achieve superior lithography performances and defect reduction. Lithographic depth of focus, critical dimension uniformity and line edge/width roughness were improved after 193 nm immersion exposure and etching for pattern transfer. Impact of the development method on defect reduction was also investigated. There was a 10x reduction in the bridging defect after patterning transfer for line/space patterning. The current work provides a strategy for positive tone development with significant defect reduction and improving our understanding of defect control from track related processing, which is of far-reaching significance for improvement in production yield for semiconductor manufacturing.

Multi-patterning techniques with ArF immersion lithography is expected to continue as main solution for manufacturing IC chips. The reduction of laser downtime has great impact on the productivity of chipmakers. The laser downtime is closely related to the lifetime of consumable parts of the laser. Gigaphoton developed new laser modules, chamber and LNM (Line Narrowing Module) which have longer lifetime than current one. New chamber demonstrated 1.2 times longer lifetime than current chamber. New LNM demonstrated 1.8 times longer lifetime than current LNM. These new modules will help to reduce the downtime of the laser.

In optical lithography, lens heating induced aberrations of a projection lens lead to degradation of imaging quality. In order to accurately compensate for thermal aberrations by integrated manipulators in projection lens, it is crucial to apply an accurate method for thermal aberration prediction. In this paper, an effective and accurate method for thermal aberration prediction is proposed. Double exponential model is simplified in respect of the timing of exposure tools, and particle filter is used to adjust the parameters of the double exponential model. Parameters of the simplified model are updated recursively pursuant to the aberration data measured during the exchange of wafers. The updated model is used to predict thermal aberrations of the lens during the following exposure of wafer. The performance of the algorithm is evaluated by simulation of a projection lens for ArF lithography. Maximum root mean square (RMS) value of perdition error of thermal aberration under annular illumination and dipolar illumination are reduced by 68.3% and 76.1%, respectively. The proposed method is also of well adaptability to different types of aberration measurement error.

As the semiconductor device dimension continues to shrink, the tolerance of Critical Dimension (CD) variation has been dramatically reduced for whole chip area to ensure the good uniformity of device functionality. Accordingly, the Optical Proximity Correction (OPC) model accuracy has become extremely important for controlling across-chip CD variation. The traditional method relying on CD Scanning Electron Microscope (CD-SEM) measurement data from synthetic patterns, such as dense line/space and isolated line in various pitch biases, for OPC model calibration is no longer sufficient for accurately projecting the complex patterns such as asymmetrical layout environments. Alternatively, the 2D extracted contours from SEM images associated with user-specified cutline algorithm to get the dimensional information of complex patterns have been incorporated for OPC modeling as well as process qualification [1-3]. In this work, the 2D contour extraction methodology was incorporated to extract more comprehensive CD information of complex features for OPC model calibration of 39nm half-pitch process layer. Together with the use of CD-SEM based CD, the model calibration via MASK2D and MASK3D model forms were conducted for accuracy comparison. The OPC model validation results demonstrated the contour-based gauges helps to improve the OPC model projection accuracy by 40~60% for asymmetrical features comparing to the traditional OPC calibration method.

A new fabrication method of micro-lens arrays with element lens diameters of 20-50 μm was developed in the past research. In the method, epoxy micro-lens arrays are replicated using concave resist patterns as molds. In this paper, resist mold pattern profiles were investigated again in detail, and model curves to be fitted to pattern cross sections were looked over again. As a result, it was found that cross section curves of resist mold patterns were very accurately modeled by decomposing each curve into three parts of a central circular concave arc, a peripheral circular convex arc, and a tangential line connecting them. For this reason, using the new fitting curves, how parallel light rays incident in an element lens were refracted at the lens surface, and concentrated in a spot were investigated. It was clarified by the ray trace that parallel light rays were efficiently concentrated in a considerably small light spots by grace of the tangential line parts. Next, the ray trace results were compared with the experimental results. A micro-lens array fabricated under the same conditions was illuminated by a parallel light ray flux. As a result, the position where the traced rays were concentrated almost coincided with the position obtained experimentally. The diameters of concentrated light spots estimated by the ray trace also almost coincided with the actually observed ones. Thus, optical characteristics of microlens arrays fabricated by the new method were adequately qualified. The new method will be useful.