Recent progress with I_DDQ testing has demonstrated the ability to identify a majority of defects in logic ICs. I_DDQ testing has also been integrated in fault simulators embedded with automatic test pattern generation algorithms to further extend defect coverage. However, this progress has not eliminated the complex task of defect localization on the silicon level of ICs. Duration and accuracy of localization have a direct impact on the cost of failure analysis. Faster, better localization means shorter failure analysis and turn around time which in turn impacts the yield and reliability of IC production lines. To respond to this challenge, a new application of I_DDQ tests has been developed to accelerate the localization task and to directly impact IC production yields and reliability. In this paper, we will present a novel voltage contrast method for high speed defect localization. Using the same test pattern as that used to identify a faulty circuit, the equipotential line of the failure can be located using only a failed circuit. Comparing the equipotential line with the fault simulator output, the site of the simulated defect corresponding to the physical failure can be extracted, and local deprocessing with a FIB can be used on the failed circuit to physically reveal the defect with an improved turn around time.

Abnormal IDDQ is the signal to indicate the presence of physical damage in a circuit. By using this phenomenon, a CAD-based fault diagnosis technique has been developed for CMOS-LSI with various leakage current state. This method of progressively reducing the faulty block works by extracting inner logic state of each block, which composes hierarchical circuit and LSI circuit, from logic simulation and by deriving test vector numbers with abnormal IDDQ. Two kinds of complex leakage state are abnormal state of LSI with penetration current from VDD to GND in normal state and with multiple faults. At the former state, test vector numbers with true abnormal IDDQ are extracted by subtracting operation between normal and unusual current value, and the latter, by classification of multiple values. The fundamental diagnosis technique employs the comparative operation of each block to determine whether the same input logic state with abnormal IDDQ exists in the input logic state with normal IDDQ or not. The former block is regarded as normal block and the latter is as faulty block. This diagnosis method for LSI with various leakage current state detects easily the faulty blocks of each abnormal IDDQ state.

Focused Ion Beam technology has two main areas of application for ICs: modification and preparation for technological analysis. The most solicited area is modification. This involves physically modifying a circuit by cutting lines and creating new ones in order to change the electrical function of the circuit. IC planar technologies have an increasing number of metal interconnections making FIB modifications more complex and decreasing their changes of success. The yield of FIB operations on ICs reflects a downward trend that imposes a greater number of circuits to be modified in order to successfully correct a small number of them. This requires extended duration, which is not compatible with production line turn around times. To respond to this problem, two solutions can be defined: either, reducing the duration of each FIB operation or increasing the success rate of FIB modifications. Since reducing the time depends mainly on FIB operator experience, insuring a higher success rate represents a more crucial aspect as both experienced and novice operators could benefit from this improvement. In order to insure successful modifications, it is necessary to control each step of a FIB operation. To do this, we have developed a new method using in situ electrical testing which has a direct impact on the yield of FIB modifications. We will present this innovative development through a real case study of a CMOS ASIC for high-speed communications. Monitoring the electrical behavior at each step in a FIB operation makes it possible to reduce the number of circuits to be modified and consequently reduces system costs thanks to better yield control. Knowing the internal electrical behavior also gives us indications about the impact on reliability of FIB modified circuits. Finally, this approach can be applied to failure analysis and FIB operations on flip chip circuits.

The Surfscan installation is used to localize defects or irregularities on the surface of wafers. To simplify, particles with an expansion of >= 0.3 micrometers are recognized as a defect. The measuring principle of the installation is based on the comparisons of periodical structures. This means that only components of the same type are allowed on the wafer. A laser beam scans the surface of the wafer in a grid pattern, whereby the light is scattered on the structures and particles are registered by a photo- multiplier which is rotated by 90 degree against the incoming laser beam. As a rule these defects are not altogether spherical-symmetrical, so that the orientation and structure of the defect affect the intensity of the light scatter. As a defect is only illuminated from one side during measurement, various intensity values can be achieved by rotating the wafer. Therefore measurements with various wafer orientations were taken to assure that a possible defect is illuminated from all four sides. By using various intensity values information can be gained about the form, size and situation of a defect. Further the information can be used to obtain an optimal recipe design of a measurement procedure, and to better define the capture rate of the installation. This results in a more effective use of the installation.

The MOS snap-back phenomenon and its temperature dependence were investigated up to 300 degrees C by measurement, parameter extraction and simulation using silicided LDD-NMOS transistors. The snap-back sustaining voltage increases from 8.25V at room temperature to 8.9V at 300 degrees C. By using extracted parameters for a simple lumped element model we explain this behavior originating from an increasing avalanche breakdown voltage and increasing exponential slope of avalanche multiplication factor compensating the increase in bipolar gain with temperature. The simulation of IV- curves on circuit level using PSPICE shows an acceptable matching to the measured IV-curves. If the extracted parameters describing snap back would be specified in process documents, circuit designers could use them to identify and solve problems related to both ESD protection circuits and EOS. The results are also relevant for high temperature operation of electronics, which is a performance issue of growing importance.

In the manufacturing of IC the yield of the process is an important factor in estimating the cost. The calculation of critical area plays a key role in helping to determine the expected yield. This paper will demonstrate the use of a system, that will evolve into an expert system which can estimate the affects of photolithography on critical area. The system transforms critical area curves generated from the mask layout to more realistic curves related to the pattern on the wafer. It has been observed that this gives improved critical area estimates.

Deep submicron technology poses many difficult challenges. One of them is the optimization of the clock rate versus sub-threshold leakage trade-off. Top speed performance demands the shortest possible channel length for all transistors in the critical paths, while the need to limit subthreshold leakage requires that no transistor violates the minimum channel length rule. The problem is that the channel length is impacted by the layout density. One cause of variations in channel length is lithography. Since the global lithography settings must be chosen to avoid excessive subthreshold leakage, some of the transistors will have non-minimum channel lengths, and therefore will be slower than necessary. It is possible to compensate for the above effect by resizing transistors on the mask. In this paper we propose a methodology for analyzing different correction schemes in terms of their impact on critical path delays. Our methodology involves transistor categorization according to local layout patterns, together with simulation-based computations of channel length as a function of the local layout pattern. A DRC-based approach is used to identify transistor categories. Lithography simulation is used for proximity effect evaluation. Circuit speed is estimated by critical path simulation. In the paper we will compare various correction schemes for one of the main functional blocks in a a state-of-the-art microprocessor.

Increasing numbers of the I/O's and higher frequency components together with miniaturization of electronic devices requires new, smaller, higher performance and cost effective packaging technologies. One promising solution to meet all these requirements is the flip chip interconnection method. Flip chip components offer excellent electrical and thermal performance and smallest possible package size. To achieve reliable and high performance flip chip interconnections the structure of the bump and the assembly process must both be optimized. Experimental results show that by using well known TiW/Au under bump metallurgy with extra layer of nickel a reliable and a high performance bump base structure for solder bumps can be achieved. If process parameters and materials used in the flip chip process are optimized, reliability of the flip chip interconnection can be excellent. This paper presents electrical and physical characteristics and temperature cycling reliability test results of solder bumped flip chip components using TiW/Au/Ni metallurgy.

Conductive adhesives are gaining interest against SnPb soldering in microelectronics assemblies. The aim of this study is to evaluate the use of conductive adhesives for industrial SMT assemblies. Hence, after a short description of the most common conductive adhesives in use, this paper presents how to settle parameters of stenciling and 'pick and place' machines ordinary used for solder joints; the temperature cure schedule of conductive adhesives is defined, and validate by physical and thermal analyses. Finally, the reliability is evaluated and failure mechanisms are pointed out.

The first global demonstration of wafer-level reliability (WLR) test structure and methodology effectiveness is in progress. This action, initiated by an organization of fabless companies and concentrated on foundry service providers, represents a market-driven effort. WLR has been discussed, evaluated, promoted and even made a requirement in semiconductor IC procurement documents. This project utilizes a common suite of WLR structures fabricated at most commercial foundries to demonstrate the effectiveness of WLR structures for use as process monitors.

Manufacturing tools may process wafers in different fashions: by group of lots, by lot, by group of wafers, one- by-one in single or multichamber tools,... The order sequence in which wafers are processed in a given step of the manufacturing routing can be used as a valuable source for yield improvement. Within this scope we published on SPIE's 1996 Microelectronic Manufacturing an Advanced Software System to correlate order-sequences versus any yield related metric. Since then we have developed a new generation of Software named POSISCAN which automates the analysis and detection of 'order patterns', that is, footprints of the yield being impacted by the order in which the wafers were processed in a specific tool. Yield degradation induced on each process can have a kind of footprint. We have accumulated a wealth of these footprints and developed a very fine knowledge-based algorithm to automatically detect them on every lot. The effectiveness of this automated POSISCAN tool is remarkably high and is having a big impact on time to detection/analysis/root-cause of yield loss.

In this paper, we propose a sequential probability ratio test based on a two parameter Weibull distribution for IC failures. The shape parameter of the Weibull distribution characterizes the decreasing, constant and the increasing failure rate regions in the bath tub model for ICs. The algorithm detects the operating region of the IC based on the observed failure times. Unlike the fixed-length test, the proposed algorithm due to its sequential nature uses the minimum average number of devices for the test for fixed error tolerances in the detection procedure. We find that the proposed test is on an average 96 percent more efficient than the fixed-length test. Our algorithm is shown to be highly robust to the variations in the model parameters unlike other existing sequential tests. Further, extensive simulations are used to validate the analytic results of the sequential test.

We have investigated the influence of silicon surface integrity (SSI) on LSI device characteristics and yield. It was found that SSI spoiling during the wafer shaping process causes the reduction of gate oxide integrity (GOI), resulting in poor yield of LSIs. We demonstrated that some analysis techniques, such as long-time SC-1 cleaning, the combination of Cu decoration method and SEM observation and optical shallow defect analyzer are effective for evaluation of SSI. By Cu decoration and SEM observation, many small pits of about 0.03 micrometers were observed at GOI failure points. In addition, a model for pit generation was also established in this study. It is thought that Cu ions from contamination takes electrons from activated Si surface in pure water, and oxidized the Si surface partly. The Cu was removed by SC-1 final cleaning, and only pits remain on the Si wafer surface. The pits were primary cause of GOI failure and abnormal LPD increase.

We report here on process integration issues in the interconnect module of advanced microprocessor. We show how stresses in certain layers can affect yield and result in novel failure mechanisms in other layers. The paper will follow the history of a yield crash from beginning to end. We show how the problem was isolated, how yields were raised once the issues were fixed, and how an understanding of the issues involved can allow us to construct a more robust process from the beginning, therefore minimizing the possibility of such problems occurring in the first pace. The particular work here involves interactions of TiN with TEOS layers, and shows how local interconnect shorting can be caused by interactions between all of these layers. Stress effects in the as deposited TEOS films, although not obvious, can play a large role in determining whether or not problems occur. We also will examine how supposedly identical tools, or even two chambers within one tool can produce dramatically different end results in terms of film properties.

In this paper we study oxide deterioration caused by metal contamination using the Mercury-probe and the Surface Photovoltage techniques. It is found that deterioration caused by metal concentration as low as approximately equals 10¹⁰ cm^-2 can be monitored performing stepped current measurements. This sensitivity makes the Mercury-probe technique attractive for fast-feedback evaluation of gate oxide integrity.

Semiconductor yield models and the targets based on these models often differ from actual yield performance. The purpose of this study is to investigate yield modeling accuracy risks and requirements for 180, 150, and 130 nm technologies. Using a 300 nm CMOS process with 4 layers of copper and conventional SiO₂ dielectric, this analysis focuses on several significant risk costs including building cost, equipment cost, floor space cost, operating cost, scrap cost, and unused capacity cost. Our analysis resulted in several observations about yield modeling error.

Faulty interlevel metal contacts are already a well known yield limiting factor in wafer processing. Yield losses at electrical wafer probe test due to single via fails have been reported several times. However, some of the latent via faults will pass the electrical wafer probe test undetected, but can fail in assembly or in real life. This will be quite expensive for the manufacturer. It is a must to prevent such bad vias or at least to detect them very early in the wafer manufacturing process to improve the 'time to money' situation for the IC-industry. The novel of this paper is a loss of function of single interlevel metal contacts during plastic packaging. This influences the final electrical test yield after packaging operation, while the electrical wafer probe test yield remains unaffected. Root cause analysis indicated that an interaction of different mechanisms led to this phenomenon.

In this study, we present a very accurate method of determining the hydrogen concentration of amorphous silicon nitride (SiN) layers by employing Fourier Transform IR Spectroscopy (FTIR). Our method comprises a very effective means of rapid and non-destructive in-line monitoring and quality control for the semiconductor industry. Amorphous SiN layers are essential for the semiconductor industry as an encapsulant for silicon integrated circuits, as a diffusion barrier for H₂O and sodium ions, as passivation films, oxidation masks, gate insulators and capacitor dielectrics, their quality being highly dependent on the hydrogen content which originates from the deposition reactants NH₃, SiH₄ and SiH₂Cl₂. In contrast to commercially available FTIR software and recommended procedures in the literature, which in principle use linear baselines to evaluate the areas of the N-H and Si-H absorbance peaks, we do a polynomial fit of the spectral background outside the absorption lines. This yields a much higher accuracy in determining the areas of the absorbance peaks and therefore the hydrogen concentration. Comparisons between the two methods of evaluation yield differences of up to 30 percent, thus emphasizing the importance of our method as advanced rapid failure analysis technique. We compare the hydrogen concentrations of SiN layers deposited by LPCVD and PECVD processes and we also show how different process parameters influence the hydrogen concentration.

In this paper, a novel interferometric method with a wide range of sensitivities, called holography quasi projection moire method, is presented. It combines the features of the varied double projection moire method and the holographic interferometry method. This technique has been used to study the various failure modes, such as spallation, delamination, 1D buckle, 2D buckle, and crush, in microelectronic packaging film/substrate modules. The experimental phenomenon and fracture mechanism for various failure modes are presented and analyzed.

An unpredictable significant microloading effect occurs between array and low photoresist ratio area when C2F6Cl2 and HBr are used as etch gas to define EPROM stack gate. Although we have examined etch time for array is enough, much poly residue still exist on those test keys with low photoresist ratio areas that lead to failure of electric parameter. On array area, polymer formed from C2F6 reactant gas trends to accumulate upon side-wall. Oppositely on the low photoresist area, there is almost not nay side-wall that can offer the medium absorbed by polymer. It will fall down and deposits upon poly surface. That will be a barrier. In the beginning, sufficient etch time often result from under- etch issue. We have modified etch time to get best optimal condition. Now, this issue does not occur any more.

Nitride LDD spacer material presents itself as a viable option for oxide spacer because of two important reasons; 1) possibility of reducing in the contact-poly spacing 2) possibility of achieving higher drive current. However, as the Si-Si₃N₄ barrier height is lower than that of Si-SiO₂, hot-carrier degradation could be worse. To overcome this problem, it has been suggested that a thin layer SiO₂ be deposited under the nitride spacer to improve the hot-carrier response. Tomohisa et al. showed that oxide LDD spacer and oxide/nitride composite spacer N- MOSFETs show better hot-carrier response than those with nitride spacer. In this paper, we show that hot-carrier degradation of P-MOSFETs with oxide/Nitride composite spacer is significantly worse than that of oxide spacer devices.

The trend in microelectronic is increasing power density of IC devices in conjunction with decreasing package size. Out of this a consideration of the thermal behavior of the package and its vicinity, caused by a strong influence of the operating temperature on the component lifetime and its reliability is needed. A better outlet of the dissipated power is necessary. The temperature distribution in a package is influenced by the heat conduction in the package, depending on the different heat conductivities of the used materials. Also convection must be taken into account. In this paper a finite element model of a SOP8 plastic mounted on a printed circuit board was investigated. The influence of the material properties of the package epoxy, the adhesive, the chip carrier and the material of the printed circuit board on the temperature distribution was investigated. Also the influence of the area covered by the adhesive on the temperature behavior and the mechanical stress was investigated.

During plasma etching, the dependence of gate oxide damage on die location and polarity of the charging voltage will yield devices with varying damage across a wafer. This paper describes a simulator capable of estimating the charging voltage across the gate oxide for any location on a wafer. This tool will enable reliability and process engineers to monitor the damage and identify regions of worst-case damage on a wafer for further testing.

An antifuse is a programmable interconnect element used in field programmable gate arrays (FPGAs). It is made up of an insulating layer sandwiched by 2 electrodes. The device is normally off and have a high resistance when unprogrammed. However, with the application of a programming voltage or current pulse, the antifuse turns into a 'fuse' of low resistance due to the breakdown of the insulator, accompanied by the formation of a conductive path or filament through the insulating layer. Metal to metal antifuse are favored for high sped and high density FPGAs because they offer low on-resistance, small device area and high reliability. In FPGAs incorporating antifuses, there are typically thousands of antifuses and their leakage currents are quite substantial, thereby leading to considerable power consumption. Leakage current, I_leakage reduction can be achieved through the discerning choice of electrodes, antifuse stack material, stack composition, thickness and film deposition process conditions amongst others. In this paper, the electrical characteristics of the amorphous silicon-based antifuse with different types of barrier layers are presented. We show that the inclusion of an in-situ top barrier layer in the a- Si:H based antifuse leads to a significant reduction in the leakage current with no appreciable increase in the programming voltage.

Historical microprocessor product trends show an increase in product frequency of 1.25x per year and a transistor count increase of 1.4x per year since the early 70's. This trend is forecast to continue over the next decade to the 0.07micrometers generation. To support the trend, challenges in lithography, transistor definition, interconnect system, and manufacturability must be overcome. Solutions to the lithography challenge,s will require successful implementation of 157 nm optical or next generation lithography. The transistor solution will require integration of sub 2.0nm gate oxides with improved gate electrode materials, improved low resistance shallow source- drain technology, advanced channel dopant engineering, and operation at or below 1.0v. Interconnect challenges will require support of 10 or more interconnect layers using lower resistivity metalization and reduced epsilon dielectric. Manufacturing challenges require support of larger die sizes, integrated at higher technology complexity, while maintaining lowest possible cost.

Recently, IBM announced the first silicon integrated circuit technology that incorporates copper on-chip wiring. This technology, which combines industry-leading CMOS ULSI devices with 6 levels of hierarchically-scaled Cu metallization, has reached the point of manufacturing, after passing the qualification tests required to prove feasibility, yield, reliability, and manufacturability. The discussion of the change from Al to Cu interconnects for ULSI encompasses a wide variety of issues. This paper attempts to address these by way of example, from the broad range of detailed studies that have been performed in the course of developing these so-called 'copper chips'. Motivational issues are covered by comparative modeling of performance aspects and cost. The technology parameters and features are shown, as well as data relating to the process integration, electrical yield and parametric behavior, early manufacturing data, high-frequency modeling and measurements, noise and clock skew. The viability of this technology is indicated by results from reliability stressing, as well as the first successful demonstrations of fully functional SRAM, DRAM, and microprocessor chips with Cu wiring. The advantages of integrated Cu wiring may be applied even more broadly in the future. An example shown here is the achievement of very high-quality integrated inductors; these may help prospects for complete integration of RF and wireless communications chips onto silicon.

This paper gives an overview of the foundry model and foundry technology trend in the future. The foundry model is a part of the natural trend toward the vertical disintegration of the semiconductor industry. Foundry technology is already in the leading pack, and will be on the leading edge from now on. Foundry technology will be market driven toward low voltage, low power, high performance, high density, and system on chip. Examples of leading-edge 0.25um logic and 0.18um and beyond process features will be used to illustrate this trend.

ULSI circuit performance is constantly increasing, in sped, functionality and device density. This performance increase is supported by the constant development of new processes and new materials, on new equipment platforms, which support the demand for improved defect density and throughput. A key challenge for equipment infrastructure to continue to support this performance acceleration is the shortening of cycle time for equipment development and new material acceptance.