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Abnormal IDDQ is the signal to indicate the presence of physical damage in a circuit. By using this phenomenon, a CAD-based fault diagnosis technique has been developed for CMOS-LSI with various leakage current state. This method of progressively reducing the faulty block works by extracting inner logic state of each block, which composes hierarchical circuit and LSI circuit, from logic simulation and by deriving test vector numbers with abnormal IDDQ. Two kinds of complex leakage state are abnormal state of LSI with penetration current from VDD to GND in normal state and with multiple faults. At the former state, test vector numbers with true abnormal IDDQ are extracted by subtracting operation between normal and unusual current value, and the latter, by classification of multiple values. The fundamental diagnosis technique employs the comparative operation of each block to determine whether the same input logic state with abnormal IDDQ exists in the input logic state with normal IDDQ or not. The former block is regarded as normal block and the latter is as faulty block. This diagnosis method for LSI with various leakage current state detects easily the faulty blocks of each abnormal IDDQ state.
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