Dr. Sean C. O'Brien Profile

Dr. Sean C. O'Brien

Senior Member/Technical Staff at Texas Instruments Inc

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Publications (12)

Proceedings Article | 13 March 2024 Presentation + Paper

Optimizing a micro electro mechanical system (MEMS) based phase-only light modulator (PLM) for improved system performance

Taylor Byrum, Kristofer Oberascher, Zachary Walker, Alex Lyubarsky, Sam Martin, Griffin Orr, William McDonald, Nathan Gilly, Sean O'Brien, Kelly Taylor, Wesley Hamlin, Patrick Oden, James Hall

Proceedings Volume 12900, 129000D (2024) https://doi.org/10.1117/12.3003885

KEYWORDS: Mirrors, Diffraction, Manufacturing, Design, Mirror surfaces, Modulators, Microelectromechanical systems, Incident light, Equipment, Digital Light Processing

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Proceedings Article | 17 March 2008 Paper

Inverse lithography as a DFM tool: accelerating design rule development with model-based assist feature placement, fast optical proximity correction and lithographic hotspot detection

Steve Prins, James Blatchford, Simon Chang, Lewis Flanagin, Scott Jessen, Sean O'Brien, Guangming Xiao, Timothy Lin, Thuc Dam, Bob Gleason

Proceedings Volume 6925, 69250E (2008) https://doi.org/10.1117/12.774581

KEYWORDS: Lithography, SRAF, Photomasks, Logic, Optical proximity correction, Lithographic illumination, Printing, Critical dimension metrology, Design for manufacturing, Model-based design

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Design rule (DR) development strategies were fairly straightforward at earlier technology nodes when node-on-node scaling could be accommodated easily by reduction of λ/NA. For more advanced nodes, resolution enhancement technologies such as off-axis illumination and sub-resolution assist features have become essential for achieving full shrink entitlement, and DR restrictions must be implemented to comprehend the inherent limitations of these techniques (e.g., forbidden pitches) and the complex and unanticipated 2D interactions that arise from having a large number of random geometric patterns within the optical ambit. To date, several factors have limited the extent to which 2D simulations could be used in the DR development cycle, including exceedingly poor cycle time for optimizing OPC and SRAF placement recipes per illumination condition, prohibitively long simulation time for characterizing the lithographic process window on large 2D layouts, and difficulty in detecting marginal lithographic sites using simulations based on discrete cut planes. We demonstrate the utility of the inverse lithography technology technique [1] to address these limitations in the novel context of restrictive DR development and design for manufacturability for the 32nm node. Using this technique, the theoretically optimum OPC and SRAF treatment for each layout are quickly and automatically generated for each candidate illumination condition, thereby eliminating the need for complex correction and placement recipes. "Ideal" masks are generated to explore physical limits and subsequently "Manhattanized" in accordance with mask rules to explore realistic process limits. Lithography process window calculations are distributed across multiple compute cores, enabling rapid full-chip-level simulation. Finally, pixel-based image evaluation enables hot-spot detection at arbitrary levels of resolution, unlike the 'cut line' approach. We have employed the ILT technique to explore forbidden-pitch contact hole printing in random logic. Simulations from cells placed in random context are used to evaluate the effectiveness of restricting pitches in contact hole design rules. We demonstrate how this simulation approach may not only accelerate the design rule development cycle, but also may enable more flexibility in design by revealing overly restrictive rules, or reduce the amount of hot-spot fixing required later in the design phase by revealing where restrictions are needed.

Proceedings Article | 4 March 2008 Paper

Rules based process window OPC

Sean O'Brien, Robert Soper, Shane Best, Mark Mason

Proceedings Volume 6925, 69251C (2008) https://doi.org/10.1117/12.772790

KEYWORDS: Optical proximity correction, Lithography, Reticles, Transistors, Semiconducting wafers, Model-based design, Data modeling, Process modeling, Failure analysis, Bridges

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Proceedings Article | 29 March 2006 Paper

Top coat or no top coat for immersion lithography?

N. Stepanenko, Hyun-Woo Kim, S. Kishimura, D. Van Den Heuvel, N. Vandenbroeck, M. Kocsis, P. Foubert, M. Maenhoudt, M. Ercken, F. Van Roey, R. Gronheid, I. Pollentier, D. Vangoidsenhoven, C. Delvaux, C. Baerts, S. O'Brien, W. Fyen, G. Wells

Proceedings Volume 6153, 615304 (2006) https://doi.org/10.1117/12.660158

KEYWORDS: Thin film coatings, Digital watermarking, Particles, Semiconducting wafers, Immersion lithography, Scanners, Water, Critical dimension metrology, Photomasks, Scatterometry

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Since the moment immersion lithography appeared in the roadmaps of IC manufacturers, the question whether to use top coats has become one of the important topics for discussions. The top coats used in immersion lithography have proved to serve as good protectors from leaching of the resist components (PAGs, bases) into the water. However their application complicates the process and may lead to two side effects. First, top coats can affect the process window and resist profile depending on the material's refractive index, thickness, acidity, chemical interaction with the resist and the soaking time. Second, the top coat application may increase the total amount of defects on the wafer. Having an immersion resist which could work without the top coat would be a preferable solution. Still, it is quite challenging to make such a resist as direct water/resist interaction may also result in process window changes, CD variations, generation of additional defects. We have performed a systematic evaluation of a large number of immersion resist and top coat combinations, using the ASML XT:1250Di scanner at IMEC. The samples for the experiments were provided by all the leading resist and top coat suppliers. Particular attention was paid to how the resist and top coat materials from different vendors interacted with each other. Among the factors which could influence the total amount of defects or CD variations on the wafer were: the material's dynamic contact angle and its interaction with the scanner stage speed, top coat thickness and intermixing layer formation, water uptake and leaching. We have examined the importance of all mentioned factors, using such analytical techniques as Resist Development Analyser (RDA), Quartz Crystal Microbalance (QCM), Mass Spectroscopy (MS) and scatterometry. We have also evaluated the influence of the pre- and pos- exposure rinse processes on the defectivity. In this paper we will present the data on imaging and defectivity performance of the resists with and without the use of top coats. So far we can conclude that top coat/resist approach used in immersion lithography needs some more improvements (i.e. process, materials properties) in order to be implemented in high volume manufacturing.

Proceedings Article | 20 March 2006 Paper

Immersion specific defect mechanisms: findings and recommendations for their control

Michael Kocsis, Dieter Van Den Heuvel, Roel Gronheid, Mireille Maenhoudt, Dizana Vangoidsenhoven, Greg Wells, Nickolay Stepanenko, Michael Benndorf, Hyun Woo Kim, Shinji Kishimura, Monique Ercken, Frieda Van Roey, S. O'Brien, Wim Fyen, Philippe Foubert, Richard Moerman, Bob Streefkerk

Proceedings Volume 6154, 615409 (2006) https://doi.org/10.1117/12.660432

KEYWORDS: Semiconducting wafers, Thin film coatings, Water, Particles, Scanners, Immersion lithography, Manufacturing, Scanning electron microscopy, Space operations, Distortion

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Proceedings Article | 17 March 2006 Paper

Improving asymmetric printing and low margin using custom illumination for contact hole lithography

Scott Jessen, Mark Terry, Mark Mason, Sean O'Brien, Robert Soper, Willie Yarbrough, Thomas Wolf

Proceedings Volume 6156, 615616 (2006) https://doi.org/10.1117/12.660120

KEYWORDS: SRAF, Printing, Optical proximity correction, Lithographic illumination, Fiber optic illuminators, Lithography, Logic devices, Photomasks, Metals, Logic

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Proceedings Article | 15 March 2006 Paper

Immersion effects on lithography system performance

Seiji Nagahara, Ivan Pollentier, Takahiro Machida, Sean O'Brien, Eric Jacobs, Charles Schaap, Philippe Leray, Greet Storms, Kathleen Nafus, David Laidler, Shaunee Cheng

Proceedings Volume 6154, 61540U (2006) https://doi.org/10.1117/12.659620

KEYWORDS: Semiconducting wafers, Thin film coatings, Scanners, Temperature metrology, Reticles, Immersion lithography, Scatterometry, Lithography, Overlay metrology, Scatter measurement

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The immersion effects on lithography-system performance have been investigated using a ASML TWINSCAN XT:1250Di immersion-ArF scanner (NA=0.85) and Tokyo Electron CLEAN TRACK ACT12 at IMEC. Effects of immersion-induced-temperature change and effects of material-top surface are discussed in this paper. The wafer-stage temperature is measured during the leveling-verification tests and compared with the observed residual-focus-error change. The results indicate that stage-temperature change under an immersion environment can induce a focus change. In this paper, it was proved that the improved-temperature-control stage is effective to mitigate the immersion-specific focus change. The immersion effect on overlay is also investigated as a function of material top surface. It was demonstrated that the effect of material-receding-contact angles on the grid-residual errors (non-correctable errors) is small in the latest-immersion-hardware configuration of the scanner. However, there was a tendency that material with a smaller-receding-contact angle has a larger-wafer scaling although it is a correctable parameter. This can be caused by the first-layer wafer shrinkage due to more water evaporation on the more-hydrophilic surface. The immersion effect on scanner-dynamic performance is then investigated by changing the material-top surface and the scan speed of the scanner. It was turned out that the scan synchronization is not much affected by differences of material receding-contact-angles for the new configuration of the scanner. Moving-standard deviation of the synchronization error in scanning direction (y-direction) is slightly more affected by increased scanning speed, although it stays within specification even at a maximum scan speed of 500 mm/sec. Finally the immersion effects on resist-profile uniformity are examined. It was found that lower-leaching-film stacks (with a top coat or a lower leaching resist) seem to mitigate the variation of resist-profile uniformity.

Proceedings Article | 12 May 2005 Paper

65nm node gate pattern using attenuated phase shift mask with off-axis illumination and sub-resolution assist features

Gary Zhang, Mark Terry, Sean O'Brien, Robert Soper, Mark Mason, Won Kim, Changan Wang, Steven Hansen, Jason Lee, Joe Ganeshan

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.600409

KEYWORDS: SRAF, Critical dimension metrology, Optical proximity correction, Photomasks, Scanners, Lithographic illumination, Semiconducting wafers, Phase shifts, Lithography, Resolution enhancement technologies

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Proceedings Article | 5 May 2005 Paper

Design rule considerations for 65-nm node contact using off axis illumination

Scott Jessen, Mark Mason, Sean O'Brien, Mark Terry, Robert Soper, Thomas Wolf

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.600005

KEYWORDS: SRAF, Printing, Photomasks, Optical proximity correction, Manufacturing, Lithography, Solids, Logic, Image resolution, Model-based design

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Proceedings Article | 10 July 2003 Paper

OPC on real-world circuitry

Sean O'Brien, Tom Aton, Mark Mason, Carl Vickery, John Randall

Proceedings Volume 5042, (2003) https://doi.org/10.1117/12.485484

KEYWORDS: Optical proximity correction, Lithography, Resolution enhancement technologies, Reticles, SRAF, Silicon, Photomasks, Transistors, Scanning electron microscopy

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Proceedings Article | 14 September 2001 Paper

Exposure latitude requirements for high yield with photon flux-limited laser sources

Sean O'Brien, Mark Mason

Proceedings Volume 4346, (2001) https://doi.org/10.1117/12.435780

KEYWORDS: Transistors, Lithography, Semiconductors, Process control, Statistical analysis, Failure analysis, Imaging systems, Transparency, Laser sources, Semiconductor lasers

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Proceedings Article | 13 September 1996 Paper

Study of integration issues in shallow trench isolation for deep submicron CMOS technologies

Amitava Chatterjee, Mark Mason, K. Joyner, Daty Rogers, Doug Mercer, John Kuehne, A. Esquivel, P. Mei, Suhail Murtaza, Kelly Taylor, Iqbal Ali, S. Nag, Sean O'Brien, S. Ashburn, Ih-Chin Chen

Proceedings Volume 2875, (1996) https://doi.org/10.1117/12.250874

KEYWORDS: Oxides, Etching, Chemical mechanical planarization, CMOS technology, Lithography, Silicon, Photomasks, Scanning electron microscopy, Chemical vapor deposition, Oxidation

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Showing 5 of 12 publications

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