Dr. Gary Zhang Profile

Dr. Gary Zhang

Director Strategic Marketing at ASML

SPIE Involvement:

Author

Publications (23)

Proceedings Article | 26 May 2022 Poster + Presentation + Paper

Advanced dose control using random logic device patterns and massive metrology in a foundry high-volume manufacturing environment

Wen Zhan Zhou, Kan Zhou, Yu Yang Bian, Yu Zhang, Ijen van Mil, Robbin Zhu, Jo Zhu, Ivan Mao, Kai yuan Chi, Xuechen Zhu, Kelvin Pao, Pei Wang, Lilla Wang, Abdalmohsen Elmalk, Gary Zhang

Proceedings Volume 12053, 120532A (2022) https://doi.org/10.1117/12.2638430

KEYWORDS: Metrology, Semiconducting wafers, Control systems, Optical proximity correction, Logic devices, Reticles, Stochastic processes, High volume manufacturing, Finite element methods, Error analysis

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One of the most critical challenges in the lithography process is to effectively control all critical patterns over the full exposure field, across wafer, and from lot to lot consistently. ASML’s advanced dose-control solutions have been widely adopted to control CDU of critical patterns. A new high-order dose-control capability is introduced with extended controllability over a larger number of patterns to mitigate the stochastic effect and optimize dies-in-spec performance. Traditionally, designed marks or patterns are placed in the die for dense metrology sampling required for the advanced high-order dose-control applications. However, this method has a few disadvantages especially for logic foundry use cases. For example, the designed marks are often not identical to random logic critical patterns, thus leading to a situation in which marks are controlled well while device patterns are not. In-die placement of the designed marks normally imposes constrains in device layout, which is not acceptable in some cases such as large-die layouts. A preferred approach would be to measure directly on device-critical and/or weak-point (WP) patterns. But this brings up another challenge in metrology of device WP patterns. With conventional CDSEM the amount of data points is limited by the tool throughput. WP patterns are typically 2D patterns, with normally a high noise contribution from local variations (due to resist stochastics) and metrology. Thus to suppress the local variations, averaging of many local measurements of 2D WP patterns is preferred. This requires a high throughput e-beam metrology tool capable of making massive amount of inline measurements within a given cycle time. To address these challenges, we have developed a method of using yield-limiting device patterns to directly control dose and thus improve CDU. Close to 100 WPs per in-die location have been selected with a dense die coverage to minimize the contribution to global CDU from the local variations and metrology noise. A high-speed e-beam metrology tool is used to measure all the selected WP patterns. A CDU budget breakdown (BB) has been analyzed to identify and quantify CDU contributors, such as reticle fingerprint, OPC error, local CDU, metrology noise, etc. Different in-die WP sampling and dose-control methods are studied in this work to achieve optimal CDU correction while keeping the metrology cycle time under control for HVM implementation.

Proceedings Article | 10 October 2019 Paper

Full-chip application of machine learning SRAFs on DRAM case using auto pattern selection

Kun-yuan Chen, Andy Lan, Richer Yang, Vincent Chen, Shulu Wang, Stella Zhang, Xiangru Xu, Andy Yang, Sam Liu, Xiaolong Shi, Angmar Li, Stephen Hsu, Stanislas Baron, Gary Zhang, Rachit Gupta

Proceedings Volume 10961, 1096108 (2019) https://doi.org/10.1117/12.2524051

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As technology continues to scale aggressively, Sub-Resolution Assist Features (SRAF) are becoming an increasingly key resolution enhancement technique (RET) to maximize the process window enhancement. For the past few technology generations, lithographers have chosen to use a rules-based (RB-SRAF) or a model-based (MB-SRAF) approach to place assist features on the design. The inverse lithography solution, which provides the maximum process window entitlement, has always been out of reach for full-chip applications due to its very high computational cost. ASML has developed and demonstrated a deep learning SRAF placement methodology, Newron™ SRAF, which can provide the performance benefit of an inverse lithography solution while meeting the cycle time requirements for full-chip applications [1]. One of the biggest challenges for a deep learning approach is pattern selection for neural network training. To ensure pattern coverage for maximum accuracy while maintaining turn-around time (TAT,) a deep-learning-based Auto Pattern Selection (APS) tool is evaluated. APS works in conjunction with Newron SRAF to provide the optimal lithography solution. In this paper, Newron SRAF is used on a DRAM layer. A Deep Convolutional Neural Network (DCNN) is trained using the target images and Continuous Transmission Mask (CTM) images. CTM images are gray tone images that are fully optimized by the Tachyon inverse mask optimization engine. Representative patterns selected by APS are used to train the neural network. The trained neural network generates SRAFs on the full-chip and then Tachyon OPC+ is performed to correct main and SRAF simultaneously. The neural network trained by APS patterns is compared with those trained by patterns from manual selection and multiple random selections to demonstrate its robustness on pattern coverage. Tachyon Hierarchical OPC+ (HScan+) is used to apply Newron SRAF at full-chip level in order to keep consistency and increase speed. Full-chip simulation results from Newron SRAF are compared with the baseline OPC flow using RBSRAF and MB-SRAF. The Newron SRAF flow shows significant improvements in NILS and PV band over the baseline flows. This whole flow including APS, Newron SRAF and full-chip HScan+ OPC enables the inverse mask optimization on full-chip level to achieve superior mask performance with production-affordable TAT.

Proceedings Article | 20 March 2018 Presentation + Paper

Efficient full-chip SRAF placement using machine learning for best accuracy and improved consistency

Shibing Wang, Stanislas Baron, Nishrin Kachwala, Chidam Kallingal, Dezheng Sun, Vincent Shu, Weichun Fong, Zero Li, Ahmad Elsaid, Jin-Wei Gao, Jing Su, Jung-Hoon Ser, Quan Zhang, Been-Der Chen, Rafael Howell, Stephen Hsu, Larry Luo, Yi Zou, Gary Zhang, Yen-Wen Lu, Yu Cao

Proceedings Volume 10587, 105870N (2018) https://doi.org/10.1117/12.2299421

KEYWORDS: SRAF, Machine learning, Optical proximity correction, Photomasks, Lithography, Model-based design, Source mask optimization, Computational lithography, Image processing

Read Abstract +

Various computational approaches from rule-based to model-based methods exist to place Sub-Resolution Assist Features (SRAF) in order to increase process window for lithography. Each method has its advantages and drawbacks, and typically requires the user to make a trade-off between time of development, accuracy, consistency and cycle time.

Rule-based methods, used since the 90 nm node, require long development time and struggle to achieve good process window performance for complex patterns. Heuristically driven, their development is often iterative and involves significant engineering time from multiple disciplines (Litho, OPC and DTCO).

Model-based approaches have been widely adopted since the 20 nm node. While the development of model-driven placement methods is relatively straightforward, they often become computationally expensive when high accuracy is required. Furthermore these methods tend to yield less consistent SRAFs due to the nature of the approach: they rely on a model which is sensitive to the pattern placement on the native simulation grid, and can be impacted by such related grid dependency effects. Those undesirable effects tend to become stronger when more iterations or complexity are needed in the algorithm to achieve required accuracy.

ASML Brion has developed a new SRAF placement technique on the Tachyon platform that is assisted by machine learning and significantly improves the accuracy of full chip SRAF placement while keeping consistency and runtime under control. A Deep Convolutional Neural Network (DCNN) is trained using the target wafer layout and corresponding Continuous Transmission Mask (CTM) images. These CTM images have been fully optimized using the Tachyon inverse mask optimization engine. The neural network generated SRAF guidance map is then used to place SRAF on full-chip. This is different from our existing full-chip MB-SRAF approach which utilizes a SRAF guidance map (SGM) of mask sensitivity to improve the contrast of optical image at the target pattern edges.

In this paper, we demonstrate that machine learning assisted SRAF placement can achieve a superior process window compared to the SGM model-based SRAF method, while keeping the full-chip runtime affordable, and maintain consistency of SRAF placement . We describe the current status of this machine learning assisted SRAF technique and demonstrate its application to full chip mask synthesis and discuss how it can extend the computational lithography roadmap.

Proceedings Article | 25 March 2016 Paper

A physical resist shrinkage model for full-chip lithography simulations

Peng Liu, Leiwu Zheng, Maggie Ma, Qian Zhao, Yongfa Fan, Qiang Zhang, Mu Feng, Xin Guo, Tom Wallow, Keith Gronlund, Ronald Goossens, Gary Zhang, Yenwen Lu

Proceedings Volume 9779, 97790Y (2016) https://doi.org/10.1117/12.2239243

KEYWORDS: Lithography, Computational lithography, Photoresist processing, Data modeling, Calibration, Cadmium, 3D modeling, Computer simulations, Optical proximity correction, Semiconducting wafers

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Proceedings Article | 19 March 2015 Paper

Holistic approach using accuracy of diffraction-based integrated metrology to improve on-product performance, reduce cycle time, and cost at litho

Kaustuve Bhattacharyya, Arie den Boef, Martin Jak, Gary Zhang, Martijn Maassen, Robin Tijssen, Omer Adam, Andreas Fuchs, Youping Zhang, Jacky Huang, Vincent Couraudon, Wilson Tzeng, Eason Su, Cathy Wang, Jim Kavanagh, Christophe Fouquet

Proceedings Volume 9424, 94241E (2015) https://doi.org/10.1117/12.2085678

KEYWORDS: Overlay metrology, Metrology, Time metrology, Target acquisition, Semiconducting wafers, Target detection, Etching, Back end of line, Scanners, Process control

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Proceedings Article | 18 March 2015 Paper

A holistic methodology to drive process window entitlement and its application to 20nm logic

Lalit Shokeen, Ayman Hamouda, Mark Terry, Dan Dechene, Stephen Hsu, Michael Crouse, Pengcheng Li, Keith Gronlund, Gary Zhang

Proceedings Volume 9427, 94270Z (2015) https://doi.org/10.1117/12.2086101

KEYWORDS: Scanners, Optical proximity correction, Source mask optimization, Process modeling, Logic, Photomasks, Semiconducting wafers, Optical lithography, Lithography, Etching

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Proceedings Article | 2 April 2014 Paper

Improving on-product performance at litho using integrated diffraction-based metrology and computationally designed device-like targets fit for advanced technologies (incl. FinFET)

Kai-Hsiung Chen, GT Huang, KS Chen, C. Hsieh, YC Chen, CM Ke, TS Gau, YC Ku, Kaustuve Bhattacharyya, Jacky Huang, Arie den Boef, Maurits v. d. Schaar, Martijn Maassen, Reinder Plug, Youping Zhang, Steffen Meyer, Martijn van Veen, Chris de Ruiter, Jon Wu, Hua Xu, Tatung Chow, Charlie Chen, Eric Verhoeven, Pu Li, Paul Hinnen, Greet Storms, Kelvin Pao, Gary Zhang, Christophe Fouquet, Takuya Mori

Proceedings Volume 9050, 90500S (2014) https://doi.org/10.1117/12.2047098

KEYWORDS: Overlay metrology, Metrology, Semiconducting wafers, Back end of line, Scanners, Diffraction, Front end of line, Process control, Etching

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Proceedings Article | 1 April 2009 Paper

Materials for single-etch double patterning process: surface curing agent and thermal cure resist

Young Bae, Yi Liu, Thomas Cardolaccia, John McDermott, Peter Trefonas, Ken Spizuoco, Michael Reilly, Amandine Pikon, Lori Joesten, Gary Zhang, George Barclay, Julia Simon, Stéphanie Gaurigan

Proceedings Volume 7273, 727306 (2009) https://doi.org/10.1117/12.814274

KEYWORDS: Double patterning technology, Photoresist processing, Image processing, Semiconducting wafers, Lithography, Photoresist materials, Cadmium, Metrology, Electron beam lithography, Coating

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Proceedings Article | 4 December 2008 Paper

BARC technology for 1.35 NA lithography

Michael Reilly, Gary Guohong Zhang, Ken Spizuoco

Proceedings Volume 7140, 71402U (2008) https://doi.org/10.1117/12.804729

KEYWORDS: Reflectivity, Reflection, Semiconducting wafers, Line edge roughness, Electron beam lithography, Lithography, Refractive index, Critical dimension metrology, Scanning electron microscopy, Diffraction

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Proceedings Article | 5 April 2007 Paper

Characterization of bending CD errors induced by resist trimming in 65 nm node and beyond

Yiming Gu, James Friedmann, Vladimir Ukraintsev, Gary Zhang, Thomas Wolf, Tom Lii, Ricky Jackson

Proceedings Volume 6518, 651826 (2007) https://doi.org/10.1117/12.714479

KEYWORDS: Critical dimension metrology, Cadmium, Semiconducting wafers, Optical proximity correction, Photoresist processing, Plasma, Silicon, Line edge roughness, Etching, Transistors

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Proceedings Article | 27 March 2007 Paper

Process window and interlayer aware OPC for the 32-nm node

Mark Terry, Gary Zhang, George Lu, Simon Chang, Tom Aton, Robert Soper, Mark Mason, Shane Best, Bill Dostalik, Stefan Hunsche, Jiang Wei Li, Rongchun Zhou, Mu Feng, Jim Burdorf

Proceedings Volume 6520, 65200S (2007) https://doi.org/10.1117/12.714442

KEYWORDS: Optical proximity correction, Metals, Photomasks, Model-based design, SRAF, Tolerancing, Critical dimension metrology, Lithography, Data modeling, Performance modeling

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Proceedings Article | 20 October 2006 Paper

Finding the needle in the haystack: using full-chip process window analysis to qualify competing SRAF placement strategies for 65 nm

Mark Mason, Shane Best, Gary Zhang, Mark Terry, Robert Soper

Proceedings Volume 6349, 63491X (2006) https://doi.org/10.1117/12.687008

KEYWORDS: SRAF, Optical proximity correction, Resolution enhancement technologies, Optical lithography, Model-based design, Silicon, Lithography, Photomasks, Semiconducting wafers, Picosecond phenomena

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Proceedings Article | 24 March 2006 Paper

Local CD variation in 65nm node with PSM processes STI topography characterization (I)

Yiming Gu, Simon Chang, Gary Zhang, Karen Kirmse, Duncan Rogers, Leif Olsen, John Lewellen

Proceedings Volume 6152, 615204 (2006) https://doi.org/10.1117/12.655914

KEYWORDS: Critical dimension metrology, Transistors, Semiconducting wafers, Cadmium, Optical proximity correction, Etching, Logic, Line edge roughness, Line width roughness, Scanning electron microscopy

Read Abstract +

How to effectively control the critical dimension (CD) is always a hot topic in photolithography. In 65nm node using phase shift mask (PSM) techniques, any factors related to CD variations should not be ignored without full investigation due to the ever-decreasing CD budget. In this paper, we focus on the local CD variation (LCDV) at the gate level within an area of 200μm x 200μm printed on a 193nm exposure tool. In contrast with AWLV (across wafer line variation) and ACLV (across chip line variation), the more localized LCDV implies that it is more dependent on the following three major factors: i) local wafer flatness mainly dominated by STI (shallow trench isolation) steps after CMP (chemical mechanical polishing); ii) effectiveness of OPC (optical proximity correction) covering all transistors with different geometrical shapes in circuit layout and iii) line edge roughness (LER) and line width roughness (LWR) related to photo and etch processes. Although OPC errors, LER and LWR are also very important, the current discussion will be limited in characterizing the relationship between LCDV and STI step-height (S-H) due to the length limitation. The STI S-H between the active surface and the trench oxide surface always exists due to the different material selectivity in the CMP process. The major gate CD influences from STI S-H are strongly correlated to the different geometrical shapes of transistors in circuits, such as single/multi-finger, wide/narrow, interior/exterior-flare and etc. According to our experiments and simulations from both alt-PSM (alternating PSM) and att-PSM (attenuating PSM) processes, the following important conclusions can be derived. a) The gate CDs in two PSM processes show different sensitivities to STI S-Hs in different geometrical shapes of transistors in circuit layout. The alt-PSM process is more sensitive than the att-PSM, especially for isolate gates. This is a shortcoming for the alt-PSM process in effectively controlling the LCDV. b) STI S-H usually makes the CD larger in both PSM processes, especially for the isolated gates in the alt-PSM process. From our observations, it is generally true that the narrower the transistor width, the higher the gate CD will be. However, CD variation trends in the att-PSM process are not so explicit as observed with alt-PSM. c) One should be very careful when trying to improve the CD uniformity by reducing STI step-height by using a blanket etch back because OPC errors are tightly combined with STI step-heights. d) Improving the STI S-H uniformity is always welcome because it will improve the AWLV. e) The narrow isolated gate is the best CD feature to monitor the interaction of AWLV with STI S-H uniformity.

Proceedings Article | 15 March 2006 Paper

Practical approach to full-field wavefront aberration measurement using phase wheel targets

Lena Zavyalova, Bruce Smith, Anatoly Bourov, Gary Zhang, Venugopal Vellanki, Patrick Reynolds, Donis Flagello

Proceedings Volume 6154, 61540Y (2006) https://doi.org/10.1117/12.657928

KEYWORDS: Data modeling, Scanning electron microscopy, Phase measurement, Calibration, Lithography, Semiconducting wafers, Photoresist materials, Photomasks, Optimization (mathematics), Error analysis

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Proceedings Article | 15 March 2006 Paper

Across wafer focus mapping and its applications in advanced technology nodes

Gary Zhang, Stephen DeMoor, Scott Jessen, Qizhi He, Winston Yan, Sopa Chevacharoenkul, Venugopal Vellanki, Patrick Reynolds, Joe Ganeshan, Jan Hauschild, Marco Pieters

Proceedings Volume 6154, 61540N (2006) https://doi.org/10.1117/12.657752

KEYWORDS: Semiconducting wafers, Sensors, Chemical mechanical planarization, Scanners, Back end of line, Monochromatic aberrations, Calibration, Process control, Front end of line, Etching

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The understanding of focus variation across a wafer is crucial to CD control (both ACLV and AWLV) and pattern fidelity on the wafer and chip levels. This is particularly true for the 65nm node and beyond, where focus margin is shrinking with the design rules, and is turning out to be one of the key process variables that directly impact the device yield. A technique based on the Phase-Shift Focus Monitor (PSFM) is developed to measure realistic across-wafer focus errors on materials processed in actual production flows. With this technique, we are able to extract detailed across-wafer focus performance at critical pattern levels from the front end of line (FEOL) all the way through the back end of line (BEOL). Typically, more than 8,000 data points are measured across a wafer, and the data are decomposed into an intra-field focus map, which captures the across chip focus variation (ACFV), and an inter-field focus map, which describes the across wafer focus variation (AWFV). ACFV and AWFV are then analyzed to understand various components in the overall focus error, including; across slit lens image field, reticle shape and dynamic scan components, local wafer flatness, wafer processing effect, pattern density, and edge die abnormality. The intra-field ACFV lens component is compared with TI's ScatterLith and ASML's FOCAL techniques. Results are consistent with the predictions based on the on-board lens aberration data. Inter-field AWFV is the most interesting, due to lack of detailed understanding of the process impact on scanner focus and leveling. PSFM data is used to characterize the effect of wafer processing such as etch, deposition, and CMP on across wafer focus control. Comparison and correlation of PSFM focus mapping with the wafer height and residual moving average (MA) maps generated by the scanner's optical leveling sensors shows a good match in general. Process induced focus errors are clearly observed on wafers of significant film stack variation and/or pattern density variation. Implications on total focus control and depth of focus (DOF) requirements for 65nm mass production are discussed in this paper using a quantitative pattern yield model. The same technique can be extended to immersion lithography.

Proceedings Article | 12 May 2005 Paper

65nm node gate pattern using attenuated phase shift mask with off-axis illumination and sub-resolution assist features

Gary Zhang, Mark Terry, Sean O'Brien, Robert Soper, Mark Mason, Won Kim, Changan Wang, Steven Hansen, Jason Lee, Joe Ganeshan

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.600409

KEYWORDS: SRAF, Critical dimension metrology, Optical proximity correction, Photomasks, Scanners, Lithographic illumination, Semiconducting wafers, Phase shifts, Lithography, Resolution enhancement technologies

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Proceedings Article | 10 May 2005 Paper

The role of AFM in semiconductor technology development: the 65 nm technology node and beyond

Vladimir Ukraintsev, Christopher Baum, Gary Zhang, Craig Hall

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.602758

KEYWORDS: Critical dimension metrology, Atomic force microscopy, Scanning electron microscopy, Line width roughness, Calibration, Metrology, Semiconductors, 3D metrology, Transmission electron microscopy, Semiconducting wafers

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Proceedings Article | 28 May 2004 Paper

Characterization of ACLV for advanced technology nodes using scatterometer-based lens fingerprinting technique

ChangAn Wang, Guohong Zhang, Stephen DeMoor, Colin Tan, John Ilzhoefer, Chris Atkinson, Chad Wickman, Steve Hansen, Bernd Geh, Donis Flagello, Mark Boehm

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.535829

KEYWORDS: Critical dimension metrology, Monochromatic aberrations, Scanners, Fiber optic illuminators, Lithography, Metrology, Semiconducting wafers, Lithographic illumination, Control systems, Solids

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Proceedings Article | 28 May 2004 Paper

Illumination source mapping and optimization with resist based process metrics for low k1 imaging

Guohong Zhang, Steve Hansen

Proceedings Volume 5377, (2004) https://doi.org/10.1117/12.536006

KEYWORDS: SRAF, Photoresist processing, Nanoimprint lithography, Fiber optic illuminators, Photomasks, Lithographic illumination, Scanners, Image processing, Printing, Lithography

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Proceedings Article | 26 June 2003 Paper

Evaluating scanner lens spherical aberration using scatterometer

Changan Wang, Gary Zhang, Colin Tan, Chris Atkinson, Mark Boehm, Jay Brown, David Godfrey, Michael Littau, Christopher Raymond

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485437

KEYWORDS: Monochromatic aberrations, Spherical lenses, Scanners, Critical dimension metrology, Optical lithography, Semiconducting wafers, Phase measurement, Scatter measurement, Scanning electron microscopy, Distortion

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Proceedings Article | 26 June 2003 Paper

Characterization of optical proximity matching for 130-nm node gate line width

Sandra Zheng, Gary Zhang, ChangAn Wang, Shangting Detweiler

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485431

KEYWORDS: Optical proximity correction, Critical dimension metrology, Metrology, Scanners, Scanning electron microscopy, Semiconducting wafers, Optical lithography, Scatterometry, Scatter measurement, Data modeling

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As IC density shrinks based on Moore’s law, optical lithography continually is scaled to print ever-smaller features by using resolution enhancement techniques such as phase shift mask, optical proximity correction (OPC), off-axis illumination and sub-resolution assistant features. OPC has been playing a key role to maximize the overlapping process window through pitch in the sub-wavelength optical lithography. As an important cost control measure, one general OPC model is applied to the full exposure field across multiple scanners. To implement this technique, optical proximity matching of line width across the field and across multiple tools turns out to be very crucial particularly at gate pattern. In addition, it is very important to obtain reliable critical dimension (CD) data sets with low noise level and high accuracy from the metrology tool. Otherwise, extracting the real scanner fingerprint in term of CD can not be achieved with precision in the order of 1nm~2nm. Scatterometry CD measurements have demonstrated excellent results to overcome this problem. The methodology of Scatterometry is emerging as one of the best metrology tool candidates in terms of gate line width control for technology nodes beyond 130nm. This paper investigates the sources of error that consume the CD budget of optical proximity matching for line through pitch (LTP). The study focuses on the 130nm technology node and uses experimental data and Prolith resist vector model based simulations. Scatterometer CD measurements of LTP are used for the first time and effectively correlated to lens aberrations and effective partial coherence (EPC) measurements which were extracted by Litel In-situ Interferometer (ISI) and Source Metrology Instrument (SMI). Implications of optical proximity matching are also discussed for future technology nodes. From the results, the paper also demonstrates the efficacy of scatterometer line through pitch measurements for OPC characterization.

Proceedings Article | 26 June 2003 Paper

Scatterometer-based scanner fingerprinting technique (ScatterLith) and its applications in image field and ACLV analysis

Changan Wang, Gary Zhang, Stephen DeMoor, Mark Boehm, Michael Littau, Christopher Raymond

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485434

KEYWORDS: Monochromatic aberrations, Scanners, Critical dimension metrology, Image analysis, Lithography, Image processing, Error analysis, Optical lithography, Manufacturing, Semiconducting wafers

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The ability to accurately, quickly and automatically fingerprint the lenses of advanced lithography scanners has always been a dream for lithographers. This is truly necessary to understand error sources of ACLV, especially when the optical lithography is pushed into 130 nm regimes and beyond. This dream has become a reality at Texas Instruments with the help of scatterometry. This paper describes the development and characterization of the scatterometer based scanner lens testing technique (ScatterLith) and its application in 193 nm and 248 nm scanner lens fingerprinting. The entire procedure includes a full field exposure through focus in a micro stepping mode, scatterometer measurement of focus matrix, image field analysis and mapping of lens curvature, astigmatism, spherical aberration, line-through pitch analysis and ACLV analysis (i.e. across chip line width variation). ACLV has been directly correlated with image field deviation, lens aberration and illumination source errors. Examples are given to illustrate its applications in accurate focus monitoring with enhanced capability of dynamic image field and lens signature mapping for the latest ArF and KrF scanners used in manufacturing environment for 130nm node and beyond. Analysis of CD variation across a full scanner field is done through a step-by-step image field correction procedure. ACLV contribution of each image field error can be quantified separately. The final across slit CD signature is further analyzed against possible errors from illumination uniformity, illumination pupil fill, and higher order projection lens aberrations. High accuracy and short cycle time make this new technique a very effective tool for in-line real time monitoring and scanner qualification. Its fingerprinting capability also provides lithography engineers a comprehensive understanding of scanner performance for CD control and tool matching. Its extendibility to 90nm and beyond is particularly attractive for future development and manufacturing requirements.

Proceedings Article | 26 June 2003 Paper

Illumination pupil fill measurement and analysis and its application in scanner V-H bias characterization for 130-nm node and beyond

Gary Zhang, Changan Wang, Colin Tan, John Ilzhoefer, Chris Atkinson, Stephen Renwick, Steve Slonaker, David Godfrey, Catherine Fruga

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485352

KEYWORDS: Scanners, Fiber optic illuminators, Critical dimension metrology, Semiconducting wafers, Metrology, Monochromatic aberrations, Printing, Data modeling, Reticles, Calibration

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A detailed characterization of across chip line width variation (ACLV) has been carried out on the latest Nikon scanners with a combination of advanced metrology techniques in Texas Instruments, including scatterometer-based image field and CD fingerprinting, lens aberrations measurement using a Litel in-situ interferometer, and illumination source imaging with a pin-hole camera. This paper describes the application of the above techniques in our investigation of the root causes for pattern CD bias between vertical and horizontal features. Illumination source radiance distribution is found sometimes to have a significant impact on V-H bias and the final overall ACLV on production wafers. Examples are given to demonstrate a comprehensive methodology that is used to quantitatively break down the overall CD errors and correlate them back to the basic optical and imaging components. It is shown through pupil-gram analysis that the ellipticity in partial coherence is typically within 1+/-1% for conventional illuminations settings on the advanced Nikon scanners while the uneven radiance distribution across the source plays a major role in V-H pattern CD bias. For scanners with low and uniform lens coma aberrations, the V-H bias after removing the contribution from image field errors is found to follow a linear relationship with the source radiance non-uniformity described also in terms of ellipticity. It is shown that radiance ellipticity is a bigger concern for off-axis illuminators. Tighter design rules patterned with off-axis illumination are more vulnerable to source radiance non-uniformity as well as lens aberrations. Illuminator induced V-H bias across the slit is compared to the signature caused by lens aberrations specifically uneven x,y-coma. Implications to exposure tool specification, control, and matching are further explored through experiments and lithography simulation for the current 130nm production and the future technology nodes in development.

Showing 5 of 23 publications

Conference Committee Involvement (4)

SPIE Lithography Asia - Taiwan

18 November 2009 | Taipei, Taiwan

SPIE Lithography Asia - Taiwan

4 November 2008 | Taipei, Taiwan

Optical Microlithography XX

27 February 2007 | San Jose, California, United States

Optical Microlithography XIX

21 February 2006 | San Jose, California, United States

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