Dr. Gerard Luk-Pat Profile

Dr. Gerard Luk-Pat

Corporate Applications Engineer at Synopsys Inc

SPIE Involvement:

Author

Publications (19)

Proceedings Article | 18 March 2015 Paper

Paper

Layout optimization with assist features placement by model based rule tables for 2x node random contact

Jinhyuck Jun, Minwoo Park, Chanha Park, Hyunjo Yang, Donggyu Yim, Munhoe Do, Dongchan Lee, Taehoon Kim, Junghoe Choi, Gerard Luk-Pat, Alex Miloslavsky

Proceedings Volume 9427, 94270D (2015) https://doi.org/10.1117/12.2085460

KEYWORDS: Atrial fibrillation, Semiconducting wafers, Photomasks, Critical dimension metrology, Optical proximity correction, Nanoimprint lithography, Lithography, Printing, SRAF, Manufacturing

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As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory and logic circuits, sub-resolution assist feature (SRAF) placement requirements become increasingly severe. Therefore device manufacturers are evaluating improvements in SRAF placement algorithms which do not sacrifice main feature (MF) patterning capability. There are known-well several methods to generate SRAF such as Rule based Assist Features (RBAF), Model Based Assist Features (MBAF) and Hybrid Assisted Features combining features of the different algorithms using both RBAF and MBAF. Rule Based Assist Features (RBAF) continue to be deployed, even with the availability of Model Based Assist Features (MBAF) and Inverse Lithography Technology (ILT). Certainly for the 3x nm node, and even at the 2x nm nodes and lower, RBAF is used because it demands less run time and provides better consistency. Since RBAF is needed now and in the future, what is also needed is a faster method to create the AF rule tables. The current method typically involves making masks and printing wafers that contain several experiments, varying the main feature configurations, AF configurations, dose conditions, and defocus conditions – this is a time consuming and expensive process. In addition, as the technology node shrinks, wafer process changes and source shape redesigns occur more frequently, escalating the cost of rule table creation. Furthermore, as the demand on process margin escalates, there is a greater need for multiple rule tables: each tailored to a specific set of main-feature configurations. Model Assisted Rule Tables(MART) creates a set of test patterns, and evaluates the simulated CD at nominal conditions, defocused conditions and off-dose conditions. It also uses lithographic simulation to evaluate the likelihood of AF printing. It then analyzes the simulation data to automatically create AF rule tables. It means that analysis results display the cost of different AF configurations as the space grows between a pair of main features. In summary, model based rule tables method is able to make it much easier to create rule tables, leading to faster rule-table creation and a lower barrier to the creation of more rule tables.

Proceedings Article | 12 April 2013 Paper

Paper

An investigation into scalability and compliance for triple patterning with stitches for metal 1 at the 14nm node

Christopher Cork, Alexander Miloslavsky, Paul Friedberg, Gerry Luk-Pat

Proceedings Volume 8683, 868308 (2013) https://doi.org/10.1117/12.2011548

KEYWORDS: Optical lithography, Metals, Photomasks, Double patterning technology, Lithography, Extreme ultraviolet lithography, Extreme ultraviolet, Legal, Network architectures, Fractal analysis

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Lithographers had hoped that single patterning would be enabled at the 20nm node by way of EUV lithography. However, due to delays in EUV readiness, double patterning with 193i lithography is currently relied upon for volume production for the 20nm node’s metal 1 layer. At the 14nm and likely at the 10nm node, LE-LE-LE triple patterning technology (TPT) is one of the favored options [1,2] for patterning local interconnect and Metal 1 layers. While previous research has focused on TPT for contact mask, metal layers offer new challenges and opportunities, in particular the ability to decompose design polygons across more than one mask. The extra flexibility offered by the third mask and ability to leverage polygon stitching both serve to improve compliance. However, ensuring TPT compliance – the task of finding a 3-color mask decomposition for a design – is still a difficult task. Moreover, scalability concerns multiply the difficulty of triple patterning decomposition which is an NP-complete problem. Indeed previous work shows that network sizes above a few thousand nodes or polygons start to take significantly longer times to compute [3], making full chip decomposition for arbitrary layouts impractical. In practice Metal 1 layouts can be considered as two separate problem domains, namely: decomposition of standard cells and decomposition of IP blocks. Standard cells typically include only a few 10’s of polygons and should be amenable to fast decomposition. Successive design iterations should resolve compliance issues and improve packing density. Density improvements are multiplied repeatedly as standard cells are placed multiple times. IP blocks, on the other hand, may involve very large networks. This paper evaluates multiple approaches to triple patterning decomposition for the Metal 1 layer. The benefits of polygon stitching, in particular, the ability to resolve commonly encountered non-compliant layout configurations and improve packing density, are weighed against the increased difficulty in finding an optimized, legal decomposition and coping with the increased scalability challenges.

Proceedings Article | 12 April 2013 Paper

Paper

Avoiding wafer-print artifacts in spacer is dielectric (SID) patterning

Gerard Luk-Pat, Ben Painter, Alex Miloslavsky, Peter De Bisschop, Adam Beacham, Kevin Lucas

Proceedings Volume 8683, 868312 (2013) https://doi.org/10.1117/12.2011539

KEYWORDS: Metals, Photomasks, Printing, Optical lithography, Dielectrics, Etching, Lithography, Double patterning technology, Semiconducting wafers, Connectors

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Proceedings Article | 13 March 2012 Paper

Paper

Design compliance for spacer is dielectric (SID) patterning

Gerard Luk-Pat, Alex Miloslavsky, Ben Painter, Li Lin, Peter De Bisschop, Kevin Lucas

Proceedings Volume 8326, 83260D (2012) https://doi.org/10.1117/12.917986

KEYWORDS: Metals, Photomasks, Dielectrics, Optical lithography, Etching, Double patterning technology, Lithography, Photoresist materials, Capacitance, Tolerancing

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Proceedings Article | 7 March 2012 Open Access

Open Access

Paper

Implications of triple patterning for 14nm node design and patterning

Kevin Lucas, Chris Cork, Bei Yu, Gerard Luk-Pat, Ben Painter, David Pan

Proceedings Volume 8327, 832703 (2012) https://doi.org/10.1117/12.920028

KEYWORDS: Optical lithography, Photomasks, Logic, Lithography, Double patterning technology, Etching, Immersion lithography, Cadmium sulfide, Metals, Dielectrics

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Proceedings Article | 10 March 2010 Paper

Paper

Process window and integration results for full-chip model-based assist-feature placement at the 32 nm node and below

Ji Li, Gerard Luk-Pat, Amyn Poonawala, Kevin Lucas, Ben Painter

Proceedings Volume 7640, 76401W (2010) https://doi.org/10.1117/12.848443

KEYWORDS: Atrial fibrillation, Optical proximity correction, Photomasks, Model-based design, Cadmium sulfide, Critical dimension metrology, Manufacturing, Printing, 3D modeling, Solids

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SPIE Journal Paper | 1 July 2009

Double-patterning interactions with wafer processing, optical proximity correction, and physical design flows

Kevin Lucas, Christopher Cork, Alexander Miloslavsky, Gerard Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Gregory Rollins, Vincent Wiaux, Staf Verhaegen

JM3, Vol. 8, Issue 03, 033002, (July 2009) https://doi.org/10.1117/12.10.1117/1.3158061

KEYWORDS: Semiconducting wafers, Double patterning technology, Lithography, Optical lithography, Etching, Photomasks, Optical proximity correction, Metals, Standards development, Critical dimension metrology

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Proceedings Article | 11 May 2009 Paper

Paper

Double patterning addressing imaging challenges for near- and sub-k1=0.25 node layouts

Beom-Seok Seo, Dae-Kwon Kang, Myung-Soo Noh, Sung-Ho Lee, Christopher Cork, Gerald LukPat, Alexander Miloslavsky, Xiaohai Li, Kevin Lucas, Sooryong Lee

Proceedings Volume 7379, 73791N (2009) https://doi.org/10.1117/12.824300

KEYWORDS: Double patterning technology, Optical proximity correction, Silicon, Optical lithography, Photomasks, Logic, Etching, Manufacturing, Metals, Lithography

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A variety of innovations including the reduction of actinic wavelength, an increase in lens NA, an introduction of immersion process, and an aggressive OPC/RET technique have enabled device shrinkage down to the current 45nm node. The immaturity of EUV and high index immersion, have made logic manufacturers look at other ways of leveraging existing exposure technologies as they strive to develop process technology for 32nm and below. For design rules for sub-nodes from 32nm to 22nm, the need to define critical layers with double photolithography and etch process becomes increasingly evident. Double patterning can come in a variety of forms or 'flavors'. For 32/28nm node, the patterning of 2D features is so challenging that opposing line-ends can only be defined using an additional litho and etch step to cut them. For 22nm node, even line/space gratings are below the theoretical k1=0.25 imaging limit. Therefore pitch-doubling double patterning decomposition is absolutely required. Each double patterning technology has its own set of challenges. Most of all, an existing design often cannot be shrunk blindly and then successfully decomposed, so an additional set of restrictions is required to make layouts double patterning compliant. To decompose a logic layout into two masks, polygons often need to be cut so that they can be patterned using both masks. The electric performance of this cut circuitry may be highly dependent on the quality of layout decomposition, the circuit characteristics and its sensitivity to misalignment between the two patterning steps. We used representative logic layouts of metal level and realistic models to demonstrate the issues involved and attempt to define formal rules to help enable lineend splitting and pitch-doubling double patterning decomposition. This study used a variety of shrink approaches to existing legacy layouts to evaluate double patterning compliance and a careful set-up of parameters for the pitch splitting decomposition engine. The quality of the resultant imaging was tuned using double patterning aware OPC and printability verification tools.

Proceedings Article | 16 March 2009 Paper

Paper

Double-patterning-friendly OPC

Xiaohai Li, Gerry Luk-Pat, Chris Cork, Levi Barnes, Kevin Lucas

Proceedings Volume 7274, 727414 (2009) https://doi.org/10.1117/12.815175

KEYWORDS: Optical proximity correction, Photomasks, Etching, Optical lithography, Double patterning technology, Semiconducting wafers, Critical dimension metrology, Model-based design, Printing, Resolution enhancement technologies

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Proceedings Article | 17 October 2008 Paper

Paper

Printability verification for double-patterning technology

Gerard Luk-Pat, Petrisor Panaite, Kevin Lucas, Christopher Cork, Vincent Wiaux, Staf Verhaegen, Mireille Maenhoudt

Proceedings Volume 7122, 71220Q (2008) https://doi.org/10.1117/12.801545

KEYWORDS: Etching, Lithography, Printing, Double patterning technology, Optical proximity correction, Critical dimension metrology, Resolution enhancement technologies, Scanning electron microscopy, Bridges, Extreme ultraviolet

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Proceedings Article | 17 October 2008 Paper

Paper

Assist feature aware double patterning decomposition

Christopher Cork, Levi Barnes, Gerard Luk-Pat

Proceedings Volume 7122, 712224 (2008) https://doi.org/10.1117/12.801562

KEYWORDS: Double patterning technology, Photomasks, Optical proximity correction, Lithography, Optical lithography, Cadmium, Tolerancing, Scanners, Critical dimension metrology, Etching

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Proceedings Article | 20 March 2008 Paper

Paper

Interactions of double patterning technology with wafer processing, OPC and design flows

Kevin Lucas, Chris Cork, Alex Miloslavsky, Gerry Luk-Pat, Levi Barnes, John Hapli, John Lewellen, Greg Rollins, Vincent Wiaux, Staf Verhaegen

Proceedings Volume 6924, 692403 (2008) https://doi.org/10.1117/12.778267

KEYWORDS: Semiconducting wafers, Optical lithography, Photomasks, Double patterning technology, Lithography, Etching, Metals, Optical proximity correction, 193nm lithography, Standards development

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Proceedings Article | 12 March 2008 Paper

Paper

Checking design conformance and optimizing manufacturability using automated double patterning decomposition

Chris Cork, Brian Ward, Levi Barnes, Ben Painter, Kevin Lucas, Gerry Luk-Pat, Vincent Wiaux, Staf Verhaegen, Mireille Maenhoudt

Proceedings Volume 6925, 69251Q (2008) https://doi.org/10.1117/12.774647

KEYWORDS: Double patterning technology, Manufacturing, Optical lithography, Photomasks, Logic, Optical proximity correction, Ultraviolet radiation, Lithography, Semiconducting wafers, Phase shifts

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Delays in equipment availability for both Extreme UV and High index immersion have led to a growing interest in double patterning as a suitable solution for the 22nm logic node. Double patterning involves decomposing a layout into two masking layers that are printed and etched separately so as to provide the intrinsic manufacturability of a previous lithography node with the pitch reduction of a more aggressive node. Most 2D designs cannot be blindly shrunk to run automatically on a double patterning process and so a set of guidelines for how to layout for this type of flow is needed by designers. While certain classes of layout can be clearly identified and avoided based on short range interactions, compliance issues can also extend over large areas of the design and are hard to recognize. This means certain design practices should be implemented to provide suitable breaks or performed with layout tools that are double patterning compliance aware. The most striking set of compliance errors result in layout on one of the masks that is at the minimum design space rather than the relaxed space intended. Another equally important class of compliance errors is that related to marginal printability, be it poor wafer overlap and/or poor process window (depth of focus, dose latitude, MEEF, overlay). When decomposing a layout the tool is often presented with multiple options for where to cut the design thereby defining an area of overlap between the different printed layers. While these overlap areas can have markedly different topologies (for instance the overlap may occur on a straight edge or at a right angled corner), quantifying the quality of a given overlap ensures that more robust decomposition solutions can be chosen over less robust solutions. Layouts which cannot be decomposed or which can only be decomposed with poor manufacturability need to be highlighted to the designer, ideally with indications on how best to resolve this issue. This paper uses an internally developed automated double pattern decomposition tool to investigate design compliance and describes a number of classes of non-conforming layout. Tool results then provide help to the designer to achieve robust design compliant layout.

Proceedings Article | 20 October 2006 Paper

Paper

Correcting lithography hot spots during physical-design implementation

Gerard Luk-Pat, Alexander Miloslavsky, Atsuhiko Ikeuchi, Hiroaki Suzuki, Suigen Kyoh, Kyoko Izuha, Frank Tseng, Linni Wen

Proceedings Volume 6349, 634920 (2006) https://doi.org/10.1117/12.692865

KEYWORDS: Model-based design, Lithography, Optical proximity correction, Metals, Resolution enhancement technologies, Semiconductors, Semiconducting wafers, Astatine, Data modeling, Process engineering

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Proceedings Article | 24 March 2006 Paper

Paper

Probabilistic calibration of a simple resist model for simulation-based scoring of mask defects

Gerard Luk-Pat, Raghava Kondepudy, Robert Du, Ray Morgan

Proceedings Volume 6152, 61522P (2006) https://doi.org/10.1117/12.656427

KEYWORDS: Semiconducting wafers, Inspection, Calibration, Photomasks, Critical dimension metrology, Printing, Wafer inspection, Cadmium, Wafer-level optics, Distortion

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Proceedings Article | 9 November 2005 Paper

Paper

Area measurements for simulation-based dispositioning of masks

Gerard Luk-Pat, Jiunn-Huang Chen, Ray Morgan, Eric Schneider

Proceedings Volume 5992, 59925C (2005) https://doi.org/10.1117/12.632182

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Image processing, Photomasks, Resistance, Scanners, Lithography, Shape analysis, Reticles, Quantization

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Proceedings Article | 20 August 2004 Paper

Paper

Photomask quality assessment solution for 90-nm technology node

Katsumi Ohira, Dong Hoon Chung, Yoshioka Nobuyuki, Motonari Tateno, Kenichi Matsumura, Jiunn-Hung Chen, Gerard Luk-Pat, Norio Fukui, Yoshio Tanaka

Proceedings Volume 5446, (2004) https://doi.org/10.1117/12.557734

KEYWORDS: Photomasks, Inspection, Semiconducting wafers, Computer simulations, Image processing, Image quality, Classification systems, Defect inspection, Resolution enhancement technologies, Deep ultraviolet

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Proceedings Article | 27 December 2002 Paper

Paper

Defect printability analysis on alternating phase-shifting masks for 193-nm lithography

Yasutaka Morikawa, Yousuke Totsu, Masaharu Nishiguchi, Morihisa Hoga, Naoya Hayashi, Linyong Pang, Gerard Luk-Pat

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.468210

KEYWORDS: Inspection, Semiconducting wafers, Photomasks, Lithography, Quartz, Dry etching, Etching, Phase shifts, Chromium, Computer simulations

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Proceedings Article | 27 December 2002 Paper

Paper

Simulation-based defect printability analysis on alternating phase-shifting masks for 193-nm lithography

Linyong Pang, Zongchang Yu, Gerard Luk-Pat, Jerry Chen, William Volk

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.468205

KEYWORDS: Photomasks, Semiconducting wafers, Inspection, Lithography, Scanning electron microscopy, Process modeling, Virtual reality, Phase shifts, Cadmium, Defect inspection

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Showing 5 of 19 publications

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