Avoiding wafer-print artifacts in spacer is dielectric (SID) patterning

Gerard Luk-Pat; Ben Painter; Alex Miloslavsky; Peter De Bisschop; Adam Beacham; Kevin Lucas

doi:10.1117/12.2011539

12 April 2013 Avoiding wafer-print artifacts in spacer is dielectric (SID) patterning

Gerard Luk-Pat, Ben Painter, Alex Miloslavsky, Peter De Bisschop, Adam Beacham, Kevin Lucas

Proceedings Volume 8683, Optical Microlithography XXVI; 868312 (2013) https://doi.org/10.1117/12.2011539
Event: SPIE Advanced Lithography, 2013, San Jose, California, United States

Abstract

For patterning the upper Metal layers of the 10 nm node, Spacer Is Dielectric (SID) Patterning is the leading candidate. Compared to Litho-Etch-Litho-Etch Double Patterning, SID has lower line-width roughness, tighter line-end spacing, and lower sensitivity to overlay errors. However, SID places more restrictions on design, and creates wafer-printing artifacts or “spurs.” These printing artifacts arise because SID uses a subtractive trim etch to create “negative contours,” which are very different from the positive contours of single-exposure patterning. In this work, we show the origin of these spurs, and present rule-based decomposition methods to avoid or mitigate them.

Citation Download Citation

Gerard Luk-Pat, Ben Painter, Alex Miloslavsky, Peter De Bisschop, Adam Beacham, and Kevin Lucas "Avoiding wafer-print artifacts in spacer is dielectric (SID) patterning", Proc. SPIE 8683, Optical Microlithography XXVI, 868312 (12 April 2013); https://doi.org/10.1117/12.2011539

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