Paper
16 March 2009 Double-patterning-friendly OPC
Author Affiliations +
Abstract
Double patterning technology (DPT) is one of the main options for printing critical layers at 32nm half-pitch and beyond. To enable DPT, a layout decomposition tool is first used to split the original design into two separate decomposed-design layouts. Each decomposed-design layout may then receive optical proximity correction (OPC) and RETs to produce a mask layout. The requirements for OPC to enable individual layer DPT patterning are generally the same as current single exposure OPC requirements, meaning that the success criteria will be similar to previous node specifications. However, there are several new challenges for OPC with DPT. These include large litho-etch biases, two sets of process variables associated with each patterning layer and the relative pattern placement between them. The order of patterning may be important as there may be process interactions between the two patterns especially at overlap regions. Corners which were rounded in single patterning layers may now become sharp, potentially increasing reliability concerns due to electromigration. In this study, we address many of these issues by proposing several new techniques that can be used in OPC with DPT. They are specifically designed for the Litho-Etch-Litho-Etch process, but some of the ideas may be extended to develop OPC methods for other DPT processes. We applied the new OPC method to several circuit and test patterns and demonstrated how OPC results were improved compared to regular OPC methods.
© (2009) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Xiaohai Li, Gerry Luk-Pat, Chris Cork, Levi Barnes, and Kevin Lucas "Double-patterning-friendly OPC", Proc. SPIE 7274, Optical Microlithography XXII, 727414 (16 March 2009); https://doi.org/10.1117/12.815175
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Cited by 6 scholarly publications.
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KEYWORDS
Optical proximity correction

Photomasks

Etching

Optical lithography

Double patterning technology

Semiconducting wafers

Critical dimension metrology

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