Mr. Cyrus E. Tabery Profile

Cyrus E. Tabery

Principle architect

SPIE Involvement:

Author

Publications (46)

Proceedings Article | 10 April 2024 Presentation + Paper

EUV OPC modeling of dry photoresist system for pitch 32nm BEOL

Jyun-Ming Chen, David Rio, Maxence Delorme, Cyrus Tabery, Christoph Hennerkes, Chris Spence, Benjamin Kam, Mohand Brouri, Nader Shamma

Proceedings Volume 12953, 129530C (2024) https://doi.org/10.1117/12.3010402

KEYWORDS: Photoresist materials, Optical proximity correction, Calibration, Semiconducting wafers, Shrinkage, Printing, Scanning electron microscopy, Photoresist developing, Metals, Critical dimension metrology

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Proceedings Article | 10 April 2024 Presentation

Computational lithography and patterning evaluation to support EUV high-NA stitching

Cyrus Tabery, Jiuning Hu, Rongkuo Zhao, Christoph Hennerkes, Stephen Hsu, Yunbo Liu, Natalia Davydova, Victor Blanco, Vincent Wiaux

Proceedings Volume PC12953, PC129530M (2024) https://doi.org/10.1117/12.3012722

KEYWORDS: Optical lithography, Reticles, Extreme ultraviolet, Process control, Critical dimension metrology, Computational lithography, Design and modelling, Optical proximity correction, Imaging systems, Tantalum

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Proceedings Article | 10 April 2024 Presentation + Paper

Overlay metrology performance of dry photoresist towards high NA EUV lithography

Eren Canga, Victor Blanco, Anne-Laure Charley, Cyrus Tabery, Gabriel Zacca, Nader Shamma, Benjamin Kam, Mohand Brouri

Proceedings Volume 12955, 129551R (2024) https://doi.org/10.1117/12.3010115

KEYWORDS: Overlay metrology, Etching, Photoresist materials, Extreme ultraviolet lithography, Lithography, Diffraction gratings, Diffraction, Reproducibility, Photoresist developing, Metrology

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Proceedings Article | 22 November 2023 Presentation

Resolution and patterning performance quantification using efficient e-beam metrology

Cyrus Tabery, Miao Wang, Victor Blanco Carballo, Eren Canga, Aiqin Jiang, Chris Spence, Tom Wallow

Proceedings Volume PC12750, PC127500B (2023) https://doi.org/10.1117/12.2688141

KEYWORDS: Electron beam lithography, Metrology, Design and modelling, Scanning laser ophthalmoscopy, Scanning electron microscopy, Line width roughness, Image enhancement, Failure analysis, Extreme ultraviolet, Etching

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Proceedings Article | 21 November 2023 Presentation + Paper

Validation of imaging benefits of dual monopole exposures

Timothy Brunner, Joern-Holger Franke, Vincent Truffert, Peter De Bisschop, Gijsbert Rispens, Edouard Duriau, Andre van Dijk, Cyrus Tabery, David Rio, Etienne De Poortere, Mark van de Kerkhof, Eric Hendrickx

Proceedings Volume 12750, 1275006 (2023) https://doi.org/10.1117/12.2685543

KEYWORDS: Semiconducting wafers, Stochastic processes, Nanoimprint lithography, Printing, Line width roughness, Simulations, Optical lithography, Extreme ultraviolet lithography, Scanning electron microscopy, Extreme ultraviolet

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Proceedings Article | 27 April 2023 Presentation + Paper

Alignment and overlay through opaque metal layers

V. Blanco Carballo, E. Canga, C. Jehoul, A. Moussa, A. Tamaddon, C. Tabery, G. Gunjala, B. Menchtchikov, V. Zacca, S. Lalbahadoersing, A. den Boef, R. Synowicki

Proceedings Volume 12496, 124960I (2023) https://doi.org/10.1117/12.2658084

KEYWORDS: Ruthenium, Optical alignment, Semiconducting wafers, Overlay metrology, Oxides, Silicon, Metals, Etching, Scanners, Copper

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SPIE Journal Paper | 13 October 2022

Predictive compact model for stress-induced on-product overlay correction

Huaichen Zhang, Cyrus Tabery, Ruben Maas, Oleksandr Khodko, Victor Blanco Carballo, Eren Canga, Filip Schleicher

JM3, Vol. 21, Issue 04, 043201, (October 2022) https://doi.org/10.1117/12.10.1117/1.JMM.21.4.043201

KEYWORDS: Semiconducting wafers, Overlay metrology, Distortion, Thin films, Optical alignment, Scanning electron microscopy, Sensors, Photomasks, Data modeling, Optical parametric oscillators

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Proceedings Article | 26 May 2022 Presentation + Paper

Absolute overlay measurement based on voltage contrast defect inspection with programmed misalignments for DRAM devices

Moosong Lee, Jinsun Kim, Dohyeon Park, Yeeun Han, Junseong Yoon, Seung Yoon Lee, Chan Hwang, Achim Woessner, Cyrus Tabery, Miao Wang, Antonio Corradi, Young-Hoon Song, Yun-A Sung, Thomas Kim, Aileen Soco, Jason Kim, Chih-Hung Hsieh

Proceedings Volume 12053, 1205315 (2022) https://doi.org/10.1117/12.2626721

KEYWORDS: Overlay metrology, Semiconducting wafers, Defect inspection, Metrology, Inspection, Standards development, Image processing, Electronics, Etching, Electrons

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Proceedings Article | 26 February 2021 Presentation + Paper

Statistical analysis of the impact of 2D reticle variability on wafer variability in advanced EUV nodes using large-scale Monte Carlo simulations

Adam Lyons, Luke Long, Tom Wallow, Chris Spence, Ton Kiers, Paul van Adrichem, Vidya Vaenkatesan, Jiyou Fu, Christoph Hennerkes, Cyrus Tabery

Proceedings Volume 11609, 116090C (2021) https://doi.org/10.1117/12.2584744

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Proceedings Article | 24 March 2020 Presentation

Holistic litho, films and etch for EUV DRAM storage node pad (Conference Presentation)

Cyrus Tabery, Nader Shamma, Nicola Kissoon, Elisabeth Camerotto, Mircea Dusa, Victor Blanco, Joost Bekaert, Rich Wise, Patrick Jaenen, Moyra McManus

Proceedings Volume 11329, 113290U (2020) https://doi.org/10.1117/12.2569606

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Proceedings Article | 16 October 2019 Presentation

Large area EUV via yield analysis for single damascene process: voltage contrast, CD and defect metrology (Conference Presentation)

Victor Blanco Carballo, Sara Paolillo, Marleen van der Veen, Stephane Lariviere, Gian Lorusso, Etienne de Poortere, Cyrus Tabery, Fu Qiao, shu-yu lai, marc kea, Luke wang, yu-chi Su, Joe Oh, jim huang, jimmy chen, jonathan huang

Proceedings Volume 11147, 111470B (2019) https://doi.org/10.1117/12.2536943

KEYWORDS: Inspection, Extreme ultraviolet, Metrology, Etching, Chemical mechanical planarization, Polishing, Logic, Optical alignment, Overlay metrology, Copper

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Proceedings Article | 26 March 2019 Presentation

Voltage contrast edge placement estimation for overlay, CD, and local uniformity metrology (Conference Presentation)

Cyrus Tabery, Vito Rutigliani, Simon Hastings, Etienne de Poortere, Luke Wang, Philippe Leray, Guillaume Schelcher, Yongjun Wang

Proceedings Volume 10959, 109591U (2019) https://doi.org/10.1117/12.2516613

KEYWORDS: Overlay metrology, Metrology, Logic, Copper, Inspection, Process modeling, Scanning electron microscopy, Wafer inspection, Error analysis, Photomasks

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Voltage contrast (VC) is a long known and well established technique to give combined inline sensitivity to electrically relevant measures of defectivity but also local defect isolation and integrated review SEM making the technique a critical piece of fab wafer inspection. By creation of a special mark design with many local repeats of different CD and overlay set points a voltage contrast response is created which allows the local edge placement error population to be estimated while also capturing a connectivity and isolation yield proxy. This enables high throughput local estimates of overlay, CD, overlay and CD process window and local CD uniformity. A test mask containing these marks was designed and fabricated at IMEC with metrology done on optical and electron beam inspection systems. Both open and short sensitivity are programmed into the marks and this yield proxy data has inherent value on its own. We propose to integrate these special test marks into some critical layers in modern memory and logic process flows with a design which can be added to scribe lines or empty regions/in die test structures in logic or empty regions of the memory periphery. Significant design and process knowledge is required to design a mark which can integrate with the process and give good EPE sensitivity. Initial mark designs have been targeted at single damascene copper on tungsten with VC inspection after copper polish. Initial results show a high baseline yield loss but also show clear and intuitive CD and Overlay process window quantification from the VC EPE marks. Marks as large as ~100,000 um2 and as small at 250um2 have been designed and enable overlay, CD, LCDU and with yield sensitivity to ~1 part per million for the larger marks and ~1% for the smallest marks. With the expected productivity of the ebeam inspection system we should be able thousands of marks per wafer or field to support diverse overlay, CD and control use models and process fingerprint mapping.

Proceedings Article | 13 March 2018 Paper

A novel patterning control strategy based on real-time fingerprint recognition and adaptive wafer level scanner optimization

Hakki Ergun Cekli, Jelle Nije, Alexander Ypma, Vahid Bastani, Dag Sonntag, Henk Niesing, Linmiao Zhang, Zakir Ullah, Venky Subramony, Ravin Somasundaram, William Susanto, Masazumi Matsunobu, Jeff Johnson, Cyrus Tabery, Chenxi Lin, Yi Zou

Proceedings Volume 10585, 105851N (2018) https://doi.org/10.1117/12.2297304

KEYWORDS: Pattern recognition, Fingerprint recognition, Semiconducting wafers, Scanners, Metrology, Overlay metrology, Optical lithography, Lithography, Manufacturing, Optical parametric oscillators, Process control, Principal component analysis

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In addition to lithography process and equipment induced variations, processes like etching, annealing, film deposition and planarization exhibit variations, each having their own intrinsic characteristics and leaving an effect, a ‘fingerprint’, on the wafers. With ever tighter requirements for CD and overlay, controlling these process induced variations is both increasingly important and increasingly challenging in advanced integrated circuit (IC) manufacturing. For example, the on-product overlay (OPO) requirement for future nodes is approaching <3nm, requiring the allowable budget for process induced variance to become extremely small. Process variance control is seen as an bottleneck to further shrink which drives the need for more sophisticated process control strategies. In this context we developed a novel ‘computational process control strategy’ which provides the capability of proactive control of each individual wafer with aim to maximize the yield, without introducing a significant impact on metrology requirements, cycle time or productivity. The complexity of the wafer process is approached by characterizing the full wafer stack building a fingerprint library containing key patterning performance parameters like Overlay, Focus, etc. Historical wafer metrology is decomposed into dominant fingerprints using Principal Component Analysis. By associating observed fingerprints with their origin e.g. process steps, tools and variables, we can give an inline assessment of the strength and origin of the fingerprints on every wafer. Once the fingerprint library is established, a wafer specific fingerprint correction recipes can be determined based on its processing history. Data science techniques are used in real-time to ensure that the library is adaptive. To realize this concept, ASML TWINSCAN scanners play a vital role with their on-board full wafer detection and exposure correction capabilities. High density metrology data is created by the scanner for each wafer and on every layer during the lithography steps. This metrology data will be used to obtain the process fingerprints. Also, the per exposure and per wafer correction potential of the scanners will be utilized for improved patterning control. Additionally, the fingerprint library will provide early detection of excursions for inline root cause analysis and process optimization guidance.

Proceedings Article | 30 March 2017 Paper

In-design and signoff lithography physical analysis for 7/5nm (Erratum)

Cyrus Tabery, Jun Ye, Yi Zou, Vincent Arnoux, Praveen Raghavan, Ryoung-han Kim, Michel Côté, Luca Mattii, Ya-Chieh Lai, Philippe Hurat

Proceedings Volume 10147, 1014705 (2017) https://doi.org/10.1117/12.2263861

KEYWORDS: Lithography, Optical proximity correction, Manufacturing, Process modeling, Design for manufacturing, Extreme ultraviolet, Data processing, Databases, Optical calibration, Model-based design, Optical lithography, Sensors, Standards development, Deep ultraviolet

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Publisher’s Note: This paper, originally published on 30-March, 2017, was replaced with a corrected/revised version on 6-April, 2017. If you downloaded the original PDF but are unable to access the revision, please contact SPIE Digital Library Customer Service for assistance.

At advanced nodes, definition of design rules and process options must be tightly optimized to deliver the best tradeoff performance, power, area and manufacturability. However, implementation platforms don’t typically have access to process information and process teams don’t have design knowledge, and optimization loops required for Design-Technology-Co-Optimization (DTCO) are either impossible or at best long and expensive for fabless design house.

Joining forces, ASML, IMEC and Cadence Design Systems developed an In-design and signoff lithography physical analysis well suited for 7/5nm and below. The Tachyon OPC+ engine used by IMEC 7/5nm process has been integrated in Cadence Litho Physical Analyzer (LPA) to perform lithography checks using the foundry process models, recipes, and hotspot detectors. This flow leverages existing LPA infrastructure for both custom and digital design platforms, as well as standalone signoff.

Depending upon the end application, LPA could be launched either from place & route or custom layout or standalone. LPA processes first the design database to identify hierarchy, decompose the layout for coloring and apply pattern matching to identify location requiring simulation. The layout is then passed to the Tachyon OPC tool to perform optical process correction and model-based litho verification that is validated on Silicon. The hotspots and contours are processed by LPA for generation of hotspot marker and fixing guidelines and provide all this information to the design environment.

The flow has been developed and demonstrated to work on IMEC 7nm, and can be ported to smaller or larger technologies. The paper will present the result of this In-design and signoff lithography physical analysis flow, how DTCO and design teams can add manufacturability to PPA.

Proceedings Article | 14 October 2011 Paper

Optimization of mask shot count using MB-MDP and lithography simulation

Gek Soon Chua, Wei Long Wang, Byoung IL Choi, Yi Zou, Cyrus Tabery, Ingo Bork, Tam Nguyen, Aki Fujimura

Proceedings Volume 8166, 816632 (2011) https://doi.org/10.1117/12.897037

KEYWORDS: Photomasks, Optical proximity correction, Lithography, Photovoltaics, Data modeling, Semiconducting wafers, SRAF, Source mask optimization, Vestigial sideband modulation, Model-based design

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Proceedings Article | 11 March 2010 Paper

Considerations in source-mask optimization for logic applications

Yunfei Deng, Yi Zou, Kenji Yoshimoto, Yuansheng Ma, Cyrus Tabery, Jongwook Kye, Luigi Capodieci, Harry Levinson

Proceedings Volume 7640, 76401J (2010) https://doi.org/10.1117/12.848865

KEYWORDS: Source mask optimization, Lithography, Photomasks, Printing, Optimization (mathematics), Logic, Photoresist processing, Process modeling, 3D modeling, Optical lithography

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Proceedings Article | 10 March 2010 Paper

Evaluation of lithographic benefits of using ILT techniques for 22nm-node

Yi Zou, Yunfei Deng, Jongwook Kye, Luigi Capodieci, Cyrus Tabery, Thuc Dam, Anthony Aadamov, Ki-Ho Baik, Linyong Pang, Bob Gleason

Proceedings Volume 7640, 76400L (2010) https://doi.org/10.1117/12.848479

KEYWORDS: Photomasks, Lithography, Source mask optimization, SRAF, Fiber optic illuminators, Metals, Optical proximity correction, Atrial fibrillation, Logic, Optimization (mathematics)

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Proceedings Article | 16 March 2009 Paper

A novel methodology for hybrid mask AF generation for 22 and 15nm technology

Yi Zou, Luigi Capodieci, Cyrus Tabery

Proceedings Volume 7274, 72741B (2009) https://doi.org/10.1117/12.814336

KEYWORDS: Atrial fibrillation, Photomasks, Lithography, Model-based design, Manufacturing, Lithium, Optical proximity correction, Resolution enhancement technologies, SRAF, Critical dimension metrology

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Mask AF (AF), both printable (PRAF) and non-printable - or sub-resolution - AF (SRAF) have been part of the established lithography and RET/OPC toolkit for achieving a manufacturable process window, for several technology generations. Deployment of AF onto a mask for a full product or test-chip layout has been traditionally rule-driven, i.e. based on look-up tables of critical feature sizes and corresponding AF, with specified dimensions and at specified distances. The number of AF per given layout main feature, the set of AF dimensions (widths, heights, etc.) and the distances (placements) from the main features are collectively referred to as the AF Rules Set. The identification of the optimal parameters values in an AF Rules Set (or the optimal AF Rules, for short) is a fundamental problem in process technology development for semiconductor manufacturing, which is typically being addressed by a mixture of heuristic parametric searches and lithographic simulations. This approach produces a limited number of usable AF rules (mainly for 1D layout configurations) and often results in insufficient coverage for 2D cases. This paper introduces a novel methodology for the determination of an optimal AF Rules set, which results in a greatly superior coverage of layout configurations (both 1D and 2D) and quantitatively verifiable larger common process window. The methodology utilizes an inverse lithography simulation step, followed by computational geometry analysis and filtering and finally automated rules extraction. The computational flow, which has been implemented for 22nm process development, delivers an order of magnitude more rules (i.e. from few tens to several hundred), and often generates non-intuitive 2D rules which could not have been discovered by heuristic search alone. The presented results illustrate the superior performance of this technique particularly in the case of contact and metal layers at 22nm. Potential extendibility of this approach for the 15nm node is also discussed.

Proceedings Article | 16 March 2009 Paper

Overcoming the challenges of 22-nm node patterning through litho-design co-optimization

Martin Burkhardt, J. C. Arnold, Z. Baum, S. Burns, J. Chang, J. Chen, J. Cho, V. Dai, Y. Deng, S. Halle, G. Han, S. Holmes, D. Horak, S. Kanakasabapathy, R. H. Kim, A. Klatchko, C. S. Koay, A. Krasnoperova, Y. Ma, E. McLellan, K. Petrillo, S. Schmitz, C. Tabery, Y. Yin, L. Zhuang, Y. Zou, J. Kye, V. Paruchuri, S. Mansfield, C. Spence, M. Colburn

Proceedings Volume 7274, 727404 (2009) https://doi.org/10.1117/12.814433

KEYWORDS: Etching, Lithography, Printing, Optical lithography, Double patterning technology, Resolution enhancement technologies, Logic, Metals, Photomasks, Tolerancing

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Proceedings Article | 16 March 2009 Paper

Contact mask optimization and SRAF design

Uwe Schroeder, Cyrus Tabery, Bradley Morgenfeld, Hideki Kanai

Proceedings Volume 7274, 727407 (2009) https://doi.org/10.1117/12.814814

KEYWORDS: SRAF, Photomasks, Critical dimension metrology, Printing, Lithography, Fiber optic illuminators, Optical proximity correction, Tolerancing, Data modeling, Optical lithography

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Proceedings Article | 16 March 2009 Paper

Inverse vs. traditional OPC for the 22nm node

James Word, Yuri Granik, Marina Medvedeva, Sergei Rodin, Luigi Capodieci, Yunfei Deng, Jongwook Kye, Cyrus Tabery, Kenji Yoshimoto, Yi Zou, Hesham Diab, Mohamed Gheith, Mohamed Habib, Cynthia Zhu

Proceedings Volume 7274, 72743A (2009) https://doi.org/10.1117/12.814339

KEYWORDS: Optical proximity correction, Photomasks, Metals, Double patterning technology, Resolution enhancement technologies, Lithography, Manufacturing, Logic, Shape analysis, Visualization

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Proceedings Article | 1 April 2008 Paper

32 nm logic patterning options with immersion lithography

K. Lai, S. Burns, S. Halle, L. Zhuang, M. Colburn, S. Allen, C. Babcock, Z. Baum, M. Burkhardt, V. Dai, D. Dunn, E. Geiss, H. Haffner, G. Han, P. Lawson, S. Mansfield, J. Meiring, B. Morgenfeld, C. Tabery, Y. Zou, C. Sarma, L. Tsou, W. Yan, H. Zhuang, D. Gil, D. Medeiros

Proceedings Volume 6924, 69243C (2008) https://doi.org/10.1117/12.784107

KEYWORDS: Photomasks, Double patterning technology, Logic, Lithography, Etching, Optical lithography, Optical proximity correction, Immersion lithography, Printing, Image processing

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The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through innovative processes. These techniques have been successfully employed for early 32nm node development using 45nm generation tooling. Four different double patterning techniques were implemented. The first process illustrates local RET optimization through the use of a split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging properties and the illumination conditions for each are independently optimized. These regions are then printed separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging with particular focus on both line-end dimension and linewidth control [1]. A double exposure-double etch (DE2) approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process, optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay tolerant [6]. Collectively, the double patterning solutions developed for early learning activities at 32nm can be extended to 22nm applications.

Proceedings Article | 26 March 2008 Paper

The use of EUV lithography to produce demonstration devices

Bruno LaFontaine, Yunfei Deng, Ryoung-Han Kim, Harry Levinson, Sarah McGowan, Uzodinma Okoroanyanwu, Rolf Seltmann, Cyrus Tabery, Anna Tchikoulaeva, Tom Wallow, Obert Wood, John Arnold, Don Canaperi, Matthew Colburn, Kurt Kimmel, Chiew-Seng Koay, Erin Mclellan, Dave Medeiros, Satyavolu Papa Rao, Karen Petrillo, Yunpeng Yin, Hiroyuki Mizuno, Sander Bouten, Michael Crouse, Andre van Dijk, Youri van Dommelen, Judy Galloway, Sang-In Han, Bart Kessels, Brian Lee, Sjoerd Lok, Brian Niekrewicz, Bill Pierson, Robert Routh, Emil Schmit-Weaver, Kevin Cummings, James Word

Proceedings Volume 6921, 69210P (2008) https://doi.org/10.1117/12.772933

KEYWORDS: Extreme ultraviolet lithography, Photomasks, Semiconducting wafers, Transistors, Extreme ultraviolet, Optical proximity correction, Photoresist processing, Etching, Metals, Scanners

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Proceedings Article | 22 March 2008 Paper

Challenges of implementing contour modeling in 32nm technology

Daniel Fischer, Geng Han, James Oberschmidt, Yong Wah Cheng, Jae Yeol Maeng, Charles Archie, Wei Lu, Cyrus Tabery

Proceedings Volume 6922, 69220A (2008) https://doi.org/10.1117/12.775444

KEYWORDS: Calibration, Scanning electron microscopy, Metrology, Optical proximity correction, Critical dimension metrology, Cadmium, Data modeling, Line edge roughness, Tolerancing, Systems modeling

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Proceedings Article | 16 November 2007 Paper

Use of layout automation and design-based metrology for defect test mask design and verification

Chris Spence, Cyrus Tabery, Andre Poock, Arndt Duerr, Thomas Witte, Jan Fiebig, Jan Heumann

Proceedings Volume 6730, 67300P (2007) https://doi.org/10.1117/12.746953

KEYWORDS: Photomasks, Semiconducting wafers, Inspection, Reticles, Optical proximity correction, Metrology, Environmental sensing, Wafer inspection, Critical dimension metrology, Defect detection

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Proceedings Article | 11 April 2007 Paper

Line-edge roughness in 193-nm resists: lithographic aspects and etch transfer

Thomas Wallow, Alden Acheta, Yuansheng Ma, Adam Pawloski, Scott Bell, Brandon Ward, Cyrus Tabery, Bruno La Fontaine, Ryoung-han Kim, Sarah McGowan, Harry Levinson

Proceedings Volume 6519, 651919 (2007) https://doi.org/10.1117/12.712319

KEYWORDS: Line edge roughness, Etching, Photoresist materials, Spatial frequencies, Lithography, Smoothing, Image processing, Critical dimension metrology, Semiconducting wafers, Photoresist processing

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Proceedings Article | 27 March 2007 Paper

SEM image contouring for OPC model calibration and verification

Cyrus Tabery, Hidetoshi Morokuma, Ryoichi Matsuoka, Lorena Page, George Bailey, Ir Kusnadi, Thuy Do

Proceedings Volume 6520, 652019 (2007) https://doi.org/10.1117/12.714389

KEYWORDS: Calibration, Scanning electron microscopy, Optical proximity correction, Data modeling, Image processing, Edge detection, Process modeling, Metrology, Critical dimension metrology, Image quality

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Lithography models for leading-edge OPC and design verification must be calibrated with empirical data, and this data is traditionally collected as a one-dimensional quantification of the features acquired by a CD-SEM. Two-dimensional proximity features such as line-end, bar-to-bar, or bar-to-line are only partially characterized because of the difficulty in transferring the complete information of a SEM image into the OPC model building process. A new method of two-dimensional measurement uses the contouring of large numbers of SEM images acquired within the context of a design based metrology system to drive improvement in the quality of the final calibrated model. Hitachi High-Technologies has continued to develop "full automated EPE measurement and contouring function" based on design layout and detected edges of SEM image. This function can measure edge placement error everywhere in a SEM image and pass the result as a design layout (GDSII) into Mentor Graphics model calibration flow. Classification of the critical design elements using tagging scripts is used to weight the critical contours in the evaluation of model fitness. During process of placement of the detected SEM edges of into the coordinate system of the design, coordinate errors inevitably are introduced because of pattern matching errors. Also, line edge roughness in 2D features introduces noise that is large compared to the model building accuracy requirements of advanced technology nodes. This required the development of contour averaging algorithms. Contours from multiple SEM images are acquired of a feature and averaged before passing into the model calibration. This function has been incorporated into the prototype Calibre Workbench model calibration flow. Based on these methods, experimental data is presented detailing the model accuracy of a 45nm immersion lithography process using traditional 1D calibration only, and a hybrid model calibration using SEM image contours and 1D measurement results. Error sources in the contouring are assessed and reported on including systematic and random variation in the contouring results.

Proceedings Article | 26 March 2007 Paper

Use of starburst patterns in optical lithography

M. Burkhardt, Cyrus Tabery

Proceedings Volume 6520, 65203O (2007) https://doi.org/10.1117/12.713274

KEYWORDS: Diffraction, Optical lithography, Diagnostics, Lithographic illumination, Optical microscopes, Fiber optic illuminators, Modulation, Lithography, Polarization, Image analysis

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Proceedings Article | 21 March 2007 Paper

Minimizing poly end cap pull back by application of DFM and advanced etch approaches for 65nm and 45nm technologies

Russell Callahan, Gunter Grasshoff, Stefan Roling, Joseph Shannon, Asuka Nomura, Sarah McGowan, Cyrus Tabery, Karla Romero

Proceedings Volume 6521, 65211Q (2007) https://doi.org/10.1117/12.712161

KEYWORDS: Etching, Chemistry, Fluorine, Chlorine, Lithography, Bromine, Line edge roughness, Manufacturing, Semiconducting wafers, Optical proximity correction

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Proceedings Article | 20 October 2006 Paper

Wafer fab mask qualification techniques and limitations

Andre Poock, Stephanie Maelzer, Chris Spence, Cyrus Tabery, Michael Lang, Guido Schnasse, Milko Peikert, Kaustuve Bhattacharyya

Proceedings Volume 6349, 63490U (2006) https://doi.org/10.1117/12.692525

KEYWORDS: Photomasks, Inspection, Semiconducting wafers, Wafer inspection, Reticles, Defect inspection, Defect detection, Wafer testing, Printing, Image resolution

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Proceedings Article | 27 March 2006 Paper

Advanced DFM applications using design-based metrology on CD SEM

G. Lorusso, L. Capodieci, D. Stoler, B. Schulz, S. Roling, J. Schramm, C. Tabery, K. Shah, B. Singh, G. Abbott, A. Roberts, A. Azordegan, L. Heinrichs, Z. Kaliblotzky, E. Castel

Proceedings Volume 6152, 61520B (2006) https://doi.org/10.1117/12.674776

KEYWORDS: Semiconducting wafers, Metrology, Optical proximity correction, Pattern recognition, Design for manufacturing, Scanning electron microscopy, Calibration, Computer aided design, Resolution enhancement technologies, Algorithm development

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Proceedings Article | 24 March 2006 Paper

Evaluation of OPC quality using automated edge placement error measurement with CD-SEM

Cyrus Tabery, Hidetoshi Morokuma, Akiyuki Sugiyama, Lorena Page

Proceedings Volume 6152, 61521F (2006) https://doi.org/10.1117/12.663017

KEYWORDS: Scanning electron microscopy, Optical proximity correction, Image processing, Image quality, Edge detection, Calibration, Metrology, Lithography, Process modeling, Image analysis

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Optical proximity correction (OPC) plays a vital role in the lithography process of cutting-edge IC fabrication. The quality of lithography models used in OPC is fundamental to the final performance of the OPC in production. Traditionally, two-dimensional proximity features such as line-end, bar-to-bar or bar-to-line were only partially characterized because of the difficulty in transferring the SEM information into the OPC model building process. A new methodology of edge placement error (EPE) measurement using CD-SEM is proposed as part of an OPC model building and process/OPC qualification flow. It is not easy to generate EPE measurements because of the inherent need to overlay the design and the SEM in order to quantify EPE. The quality of the EPE measurement depends on both the accuracy of the SEM image scan rotation and magnification, but also on the accuracy of pattern matching between the design layout pattern and the realized pattern (wafer). These problems do not exist in simulation, but model calibration requires a direct comparison between simulation and measurement. Measuring EPE effectively brings the measurement information into the realm of the design. Hitachi High-Technologies has developed a "fully automated EPE measurement function" based on design layout and detected edges of SEM image as a solution to this issue. This study shows several practical evaluation results using the automated EPE measurement function. The applications that will be discussed are as follows. 1) Design based classification of edges and subsequent quantification of SEM EPE for many types of edge arrangement and orientation. In this study, we will examine line-end-adjacent, line-end, corner, and other critical gate edges. 2) SEM image based classification of EPE fliers as a new population of errors. 3) Comparison between the detected edge of the feature within the SEM image and a polygon shape generated by lithography simulation to determine the quality of the simulation. 4) Conversion of the SEM image edge contour into an OASIS file and construction of a process variability band to quantify CD variability for all 2D contexts in a SEM image.

Proceedings Article | 12 May 2005 Paper

Design restrictions for patterning with off-axis illumination

Itty Matthew, Cyrus Tabery, Todd Lukanc, Marina Plat, Makoto Takahashi, Amada Wilkison

Proceedings Volume 5754, (2005) https://doi.org/10.1117/12.606444

KEYWORDS: Cadmium sulfide, Optical lithography, Optical proximity correction, Diffraction, Transistors, Critical dimension metrology, Lithography, Photomasks, Resolution enhancement technologies, Lithographic illumination

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Proceedings Article | 10 May 2005 Paper

Use of design pattern layout for automatic metrology recipe generation

Cyrus Tabery, Lorena Page

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.610663

KEYWORDS: Scanning electron microscopy, Computer aided design, Metrology, Semiconducting wafers, Optical proximity correction, Pattern recognition, Inspection, Lithography, Resolution enhancement technologies, Photomasks

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As critical dimension control requirements become more challenging, due to complex designs, aggressive lithography, and the constant need to shrink,metrology recipe generation and design evaluation have also become very complex. Hundreds of unique sites must be measured and monitored to ensure good device performance and high yield. The use of the design and layout for automated metrology recipe generation will be critical to that challenge. The DesignGauge from Hitachi implements a system enabling arbitrary recipe generation and control of SEM observations performed on the wafer, based only on the design information. This concept for recipe generation can reduce the time to develop a technology node from RET and design rule selection, through OPC model calibration and verification, and all the way to high volume manufacturing. Conventional recipe creation for a large number of measurement targets requires a significant amount of engineering time. Often these recipes are used only once or twice during mask and process verification or OPC calibration data acquisition. This process of manual setup and analysis is also potentially error prone. CD-SEM recipe creation typically requires an actual wafer, so the recipe creation cannot occur until the scanner and reticle are in house. All of these problems with conventional CD SEM lead to increased development time and reduced final process quality. The new model of CD-SEM recipe generation and management utilizes design-to-SEM matching technology. This new technology extracts an idealized shape from the designed pattern, and utilizes the shape information for pattern matching. As a result, the designed pattern is used as basis for the template instead of the actual SEM image. Recipe creation can be achieved in a matter of seconds once the target site list is finalized. The sequence of steps for creating a recipe are: generate a target site list, pass the design polygons (GDS) and site list to the CD SEM, define references, wafer map, and across wafer sampling, generate recipe. Utilizing this new technology, we can expect improved CD-SEM utilization and overall productivity defined by measurements acquired per unit time and by number of recipes that can be created. In addition, the control of recipe generation is improved as this automated data flow reduces the opportunities for errors. Finally, recipe creation automation can improve the time for production and development by enabling preparation before wafers get to the critical metrology steps. This is especially true in a development or foundry environment where the metrology recipe locations are updated frequently. A system is demonstrated where CDs and images can be acquired based on automated recipe generation, pattern recognition using the design polygons, and the measured CDís compared to the target CDís derived from the design. In addition, the presence of the design enables advanced information extraction such as edge placement error (EPE) in addition to traditional CD measurement. Example images and CD control analysis are presented for a critical resist inspection steps (poly, metal, and contact) and an etched poly pattern where an underlying layer is visible in SEM and used as part of the pattern matching template.

Proceedings Article | 10 May 2005 Paper

Design-based metrology: advanced automation for CD-SEM recipe generation

C. Tabery, L. Capodieci, C. Haidinyak, K. Shah, M. Threefoot, B. Choo, B. Singh, Y. Nehmadi, C. Ofek, O. Menadeva, A. Ben-Porath

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.601143

KEYWORDS: Optical proximity correction, Metrology, Computer aided design, Semiconducting wafers, Resolution enhancement technologies, Reticles, Calibration, Photomasks, Scanning electron microscopy, Data modeling

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The procedure for properly implementing OPC for a new technology node or chip design involves multiple steps: selection of the RET (resolution enhance technique), selection of design rules, OPC Model Building, OPC Verification, CD control quantification (across chip, reticle, wafer, focus, exposure, etc), calibration of Optical Rule Checks (ORC), and other verification steps. Many of these steps require up to thousands of wafer measurements, and while state-of-the-art CD-SEM tools provide automated metrology for production, manually creating a CD recipe with thousands of unique sites is extremely tedious and error-prone. This places a practical limit on both the quality and number of measurements that can be acquired during the technology development and qualification period. At the same time, the number of measurements required to qualify a new reticle design has increased drastically due to the growing complexity of RET and diminishing tolerances. To meet this challenge, a direct and automated link from the design systems to the process metrology tools is needed. Novel methodologies must also be developed to enable automated generation of teh recipe from the design inputs and to translate the flood of metrology results into information that can improve the design, mask data processing, or the patterning process. To facilitate this two-way data flow, a new framework has been created enabling true Design-Based Metrology (DBM), and an application named OPC-Check has been developed to operate within this framework. This DBM framework provides the common language and interface that facilitates the direct transfer of desired measurement locations from teh design to the metrology tool. This link is a critical element in Design for Manufacturability (DFM) efforts, a central theme in many presentations at Microlithography 2005. This article discusses the significant benefits of the tight integration of design and process metrology for OPC implementation in a new technology node, and provides some examples of the novel OPC-Check application as currently implemented at AMD SDC with Applied Materials CD-SEM tools.

Proceedings Article | 5 May 2005 Paper

A novel design-process optimization technique based on self-consistent electrical performance evaluation

Valery Axelrad, Andrei Shibkov, Gene Hill, Hung-Jen Lin, Cyrus Tabery, Dan White, Victor Boksha, Randy Thilmany

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.600283

KEYWORDS: Device simulation, Transistors, Manufacturing, Design for manufacturing, Light sources, Lithography, Optical proximity correction, Field effect transistors, Process modeling, Critical dimension metrology

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Proceedings Article | 6 December 2004 Paper

Applications using 2D contact CDSEM images

Chris Haidinyak, Cyrus Tabery

Proceedings Volume 5567, (2004) https://doi.org/10.1117/12.568906

KEYWORDS: Scanning electron microscopy, Image processing, Image filtering, Optical proximity correction, Finite element methods, Detection and tracking algorithms, Line edge roughness, Critical dimension metrology, Metrology, Image analysis

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Proceedings Article | 27 December 2002 Paper

Comparison of DUV wafer and reticle lithography: What is the resolution limit?

Chris Spence, Cyrus Tabery, Gerald Cantrell, Leslie Dahl, Peter Buck, William Wilkinson

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.468094

KEYWORDS: Semiconducting wafers, Photomasks, Reticles, Image processing, Lithography, Etching, Photoresist processing, Absorption, Reflectivity, Optical proximity correction

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Proceedings Article | 11 March 2002 Paper

ArF (193-nm) alternating aperture PSM quartz defect repair and printability for 100-nm node

Jerry Chen, John Riddick, Matt Lamantia, Azeddine Zerrade, Robert Henderson, Greg Hughes, Cyrus Tabery, Khoi Phan, Chris Spence, Amy Winder, William Stanton, Eugene Delarosa, John Maltabes, Cecilia Philbin, Lloyd Litt, Anthony Vacca, Scott Pomeroy

Proceedings Volume 4562, (2002) https://doi.org/10.1117/12.458362

KEYWORDS: Quartz, Photomasks, Semiconducting wafers, Scanning electron microscopy, Etching, Atomic force microscopy, Ions, Reticles, Inspection, Critical dimension metrology

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Proceedings Article | 14 September 2001 Paper

Evaluation of 3D alternating PSM structures using mask topography simulation, and AIMS at lambda=193nm

Cyrus Tabery, Chris Spence

Proceedings Volume 4346, (2001) https://doi.org/10.1117/12.435743

KEYWORDS: Photomasks, Etching, Quartz, Solids, Cadmium, Error analysis, Phase shifts, Critical dimension metrology, Lithography, Phase shifting

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Proceedings Article | 24 August 2001 Paper

Rational design of bleachable nonchemically amplified DUV photoactive compounds

Benjamen Rathsack, Peter Tattersall, Cyrus Tabery, Kathleen Lou, Timothy Stachowiak, David Medeiros, Jeff Albelo, Peter Pirogovsky, Dennis McKean, C. Grant Willson

Proceedings Volume 4345, (2001) https://doi.org/10.1117/12.436887

KEYWORDS: Picture Archiving and Communication System, Deep ultraviolet, Chromophores, Photoresist processing, Lithography, Absorbance, Molecules, Mask making, Photomasks, Hydrogen

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Proceedings Article | 22 January 2001 Paper

Characterization of an acetal-based chemically amplified resist for 257-nm laser mask fabrication

Benjamen Rathsack, Cyrus Tabery, Jeff Albelo, Peter Buck, C. Grant Willson

Proceedings Volume 4186, (2001) https://doi.org/10.1117/12.410739

KEYWORDS: Photomasks, Chromium, Reflectivity, Oxides, Absorption, Refraction, Chemically amplified resists, Lithography, Photoresist processing, Mask making

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Proceedings Article | 23 June 2000 Paper

Simulation-based formulation of a nonchemically amplified resist for 257-nm laser mask fabrication

Benjamen Rathsack, Cyrus Tabery, Timothy Stachowiak, Jeff Albelo, C. Grant Willson

Proceedings Volume 3999, (2000) https://doi.org/10.1117/12.388345

KEYWORDS: Picture Archiving and Communication System, Lithography, Quantum efficiency, Absorbance, Photomasks, Photoresist developing, Photoresist materials, Deep ultraviolet, Photoresist processing, Refraction

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The demand for smaller and more uniform features on photomasks has inspired consideration of a DUV (257 nm) resist process for optical pattern generation. Chemically amplified resists require storage and exposure in carbon filtered environments, and they require post-exposure bakes. Few mask facilities are set up to handle chemically amplified resists commonly used in deep UV wafer fabrication process. Hence, it is appropriate to explore the lithographic performance of non-chemically amplified resist materials for 257 nm laser photomask lithography. Resist characterization and lithography simulation were used to formulate a 257 nm resist from DNQ/novolak materials provided by a commercial resist supplier. Diazonaphthoquinone (DNQ)/novolak resists have not been used for DUV Integrated Circuit (IC) applications mainly due to the low sensitivity and the strong absorbance of the DNQ photoactive compound (PAC) at 248 nm. However, a 2,1,4 DNQ based resist has been characterized that bleaches at 257 nm and inhibits novolak. The photoproduct of the 2,1,4 DNQ PAC is much more transparent at 257 nm than 248 nm. Novolak resin also has an absorbance minimum in the DUV at 257 nm that provides transparency similar to poly (hydroxystyrene). Traditional photoresist formulation requires tedious, iterative, and expensive manufacturing trials. Resist characterization and lithography simulation can be used to relate lithographic performance (resolution, sidewall and process latitude) to resist formulation parameters (PAC concentration, developer concentration, etc.), thereby supporting the formulation optimization. An exposure system using a 257 nm frequency doubled argon laser system has been constructed to study the resist photokinetics. Dill exposure parameters (A, B and C) have been extracted for a 2,1,4 DNQ/novolak based resist. Dissolution rate measurements have been made with a development rate monitor developed at the University of Texas at Austin. Simulation using the exposure and development rate models were used to determine the resist formulation that maximizes the sidewall angle and exposure latitude for isolated resist spaces. Preliminary experiments reveal that a DNQ/novolak resist is capable of resolving 0.30 micrometer linewidths using a 257 nm optical pattern generator.

Proceedings Article | 30 December 1999 Paper

Characterization of a non-chemically amplified resist for photomask fabrication using a 257-nm optical pattern generator

Benjamen Rathsack, Cyrus Tabery, Timothy Stachowiak, Tim Dallas, Cheng-Bai Xu, Mike Pochkowski, C. Grant Willson

Proceedings Volume 3873, (1999) https://doi.org/10.1117/12.373362

KEYWORDS: Picture Archiving and Communication System, Photomasks, Absorption, Lithography, Absorbance, Transparency, Deep ultraviolet, Photoresist processing, Photoresist developing, Mask making

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I-line optical pattern generators using non-chemically amplified resists have become the workhorses for high throughput mask fabrication. The demand for smaller and more uniform features on photomasks has driven the development of a 257 nm optical pattern generator. A non-chemically amplified resist is being developed to maximize the performance of this new 257 nm mask tool. Resist characterization and lithography simulation are being used to formulate a non-chemically amplified resist for 257 nm optical pattern generators. Non- chemically amplified resists are advantageous for us in mask fabrication due to their storage and post-exposure stability. Chemically amplified resists may provide higher performance but they also require environmental mini-environments and a post-exposure bake equipment not commonly present in mask houses. Diazonaphthoquinone (DNQ)/novolak resists have not been used for DUV Integrated Circuit (IC) applications mainly due to the low sensitivity and the strong absorbance of the DNQ photoactive compound (PAC) at 248 nm. However, a 2,1,4 DNQ based resist has been characterized that bleaches at 257 nm and inhibits novolak. The photoproduct of the 2,1,4 DNQ PAC is much more transparent at 257 nm than 248 nm. Novolak resin is too strongly absorbing for use in formulating efficient 248 nm resists, but novolak has an absorbance minimum at 257 nm that provides transparency similar to poly (hydroxystyrene). Lithography simulation is being used to develop a non- chemically amplified resist to minimize the expensive iteration of manufacturing trials. An exposure system using a 257 nm frequency double Ar laser system has been constructed to study the resist photokinetics. Dill exposure parameters (A, B and C) have been extracted for a 2,1,4 DNQ/novolak based resist. Dissolution rate measurements have been made with a DRM developed at the University of Texas at Austin. Simulation is used to determine the optimal resist absorption, bleaching, dose and dissolution properties to maximize resolution. It is possible to formulate a high performance resist for 257 nm if care is taken in optimization of the formulation.

Proceedings Article | 30 December 1999 Paper

Lithography simulation of sub-0.30-um resist features for photomask fabrication using i-line optical pattern generators

Benjamen Rathsack, Cyrus Tabery, Cecilia Philbin, C. Grant Willson

Proceedings Volume 3873, (1999) https://doi.org/10.1117/12.373343

KEYWORDS: Photomasks, Reflectivity, Antireflective coatings, Reflection, Photoresist processing, Interfaces, Photoresist materials, Refraction, Coating, Chromium

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The inorganic antireflection coating (AR3-chromium oxide) commonly used on photomask blanks was designed to minimize flare in h-line (405 nm) lithography steppers. The reflection of light (flare) off this coating (air-photomask) increases with shorter exposure wavelengths. High levels of flare occur in 248 nm and 193 nm IC steppers due to reflections off of the photomask surface. The reflections (standing waves) in photomask resists also increase during exposure using lower wavelengths of light. Lithography simulations and photomask manufacturing trials have led to resist processes that can generate sub-0.30 micron resist features on photomasks with I- line optical pattern generators (ALTA 3500). Lower developer concentration, higher exposure doses and the minimization of standing waves by incorporating a post-exposure bake and/or organic antireflection coatings (ARC) maximizes resolution. High resolution photoresists show standing waves on photomasks fabricated with optical pattern generators. Low contrast resist processes show only small standing waves or in certain cases resist 'footing.' The use of organic antireflection coatings can minimize standing waves and allow the use of high contrast resist processes. ARCs reduce the swing ratio, which improves linewidth uniformity. ARCs also improve the adhesion of the resist to the photomask surface. Simulations reveal that the optimal ARC coating thickness is around 46 nm for typical I-line systems and around 50 nm for 257 nm non- chemically amplified photomask resists. Preliminary I-line photomask manufacturing trials have been done with bottom antireflection coatings at the DPI Reticle Technology Center. The first process trials reveal that the standing waves in high resolution resists were reduced but not removed. Very precise control of the ARC thickness must be exercised to completely extinguish standing waves and careful film thickness optimization appears to be necessary to minimize these reflections.

Proceedings Article | 11 June 1999 Paper

Optical lithography simulation and photoresist optimization for photomask fabrication

Benjamen Rathsack, Cyrus Tabery, Steven Scheer, Mike Pochkowski, Cecilia Philbin, Franklin Kalk, Clifford Henderson, Peter Buck, C. Grant Willson

Proceedings Volume 3678, (1999) https://doi.org/10.1117/12.350173

KEYWORDS: Photomasks, Refraction, Lithography, Picture Archiving and Communication System, Data modeling, Photoresist materials, Device simulation, Chromium, Photoresist processing, Optical simulations

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