Extreme ultraviolet (EUV) e-beam patterned mask inspection (EBPMI) has been proposed by Applied Materials as a
cost-effective solution for high volume manufacturing (HVM) in mask shops and fabs. Electron beam inspection
technology is currently available for wafers. A recent publication described a successful sensitivity study of EUVs mask
using a technology demonstration platform. Here we present a new study using extreme e-beam conditions to show the
feasibility of using EBPMI in HVM. We examine potential changes in the reflectivity at the EUV wavelength after
exposure to high e-beam currents, demonstrating that reflectivity does not change due to e-beam scanning. We therefore
conclude that under the conditions tested, which include typical as well as extreme conditions, there is no evidence of
mask damage.
Extreme ultraviolet (EUV) e-beam patterned mask inspection (EBPMI) has been proposed by Applied Materials as a
cost-effective solution for high volume manufacturing (HVM) in mask shops and fabs. Electron beam inspection
technology is currently available for wafers. A recent publication described a successful sensitivity study of EUVs mask
using a technology demonstration platform. Here we present a new study using extreme e-beam conditions to show the
feasibility of using EBPMI in HVM. We examine potential changes in the reflectivity at the EUV wavelength after
exposure to high e-beam currents, demonstrating that reflectivity does not change due to e-beam scanning. We therefore
conclude that under the conditions tested, which include typical as well as extreme conditions, there is no evidence of
mask damage.
The semiconductor industry is under constant pressure to reduce production costs even as the complexity of technology
increases. Lithography represents the most expensive process due to its high capital equipment costs and the
implementation of low-k1 lithographic processes, which have added to the complexity of making masks because of the
greater use of optical proximity correction, pixelated masks, and double or triple patterning. Each of these mask
technologies allows the production of semiconductors at future nodes while extending the utility of current immersion
tools.
Low-k1 patterning complexity combined with increased data due to smaller feature sizes is driving extremely long mask
write times. While a majority of the industry is willing to accept times of up to 24 hours, evidence suggests that the write
times for many masks at the 22 nm node and beyond will be significantly longer.
It has been estimated that funding on the order of $50M to $90M for non-recurring engineering (NRE) costs will be
required to develop a multiple beam mask writer system, yet the business case to recover this kind of investment is not
strong. Moreover, funding such a development poses a high risk for an individual supplier. The structure of the mask
fabrication marketplace separates the mask writer equipment customer (the mask supplier) from the final customer
(wafer manufacturer) that will be most effected by the increase in mask cost that will result if a high speed mask writer is
not available. Since no individual company will likely risk entering this market, some type of industry-wide funding
model will be needed.
Microelectronics industry leaders consistently cite the cost and cycle time of mask technology and mask supply as top
critical issues. A survey was designed with input from semiconductor company mask technologists and merchant mask
suppliers and support from SEMATECH to gather information about the mask industry as an objective assessment of its
overall condition. This year's assessment was the ninth in the current series of annual reports. Its data were presented in
detail at BACUS, and the detailed trend analysis is presented at EMLC. With continued industry support, the report can
be used as a baseline to gain perspective on the technical and business status of the mask and microelectronics industries.
The report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask industry.
Results will be used to guide future investments in critical path issues. This year's survey is basically the same as the
2005 through 2010 surveys. Questions are grouped into six categories: General Business Profile Information, Data
Processing, Yields and Yield Loss Mechanisms, Delivery Times, Returns, and Services. Within each category are
multiple questions that ultimately create a detailed profile of both the business and technical status of the critical mask
industry.
A survey created supported by SEMATECH and administered by David Powell Consulting was sent to microelectronics industry leaders to gather information about the mask industry as an objective assessment of its overall condition. The survey was designed with the input of semiconductor company mask technologists and merchant mask suppliers. This year's assessment is the ninth in the current series of annual reports. With ongoing industry support, the report can be used as a baseline to gain perspective on the technical and business status of the mask and microelectronics industries. It will continue to serve as a valuable reference to identify the strengths and opportunities of the mask industry. The results will be used to guide future investments pertaining to critical path issues. This year's survey was basically the same as the 2005 through 2009 surveys. Questions are grouped into categories: General Business Profile Information, Data Processing, Yields and Yield Loss Mechanisms, Delivery Times, Returns, and Services. Within each category are multiple questions that result in a detailed profile of both the business and technical status of the critical mask industry. This profile combined with the responses to past surveys represents a comprehensive view of changes in the industry.
SEMATECH has identified the need for a high resolution photomask pattern placement metrology tool to support
SEMATECH member companies' photomask production as well as research and development work. Performance
measures of the tool are driven by double exposure/double patterning approaches that will help extend 193nm
lithography according to International Technology Roadmap for Semiconductors (ITRS) requirements. Based on its
superior and extendable concept, PROVETM, a new photomask registration and overlay metrology system from Carl
Zeiss SMS, was chosen as the winning proposal for tool development by an evaluation team of mask makers and
SEMATECH member companies. The scope of the PROVETM project is to design and build a photomask pattern
placement metrology tool to serve the 32 nm node and below. The tool is designed for 193 nm illumination and imaging
optics, which enable at-wavelength metrology for current photomask needs. The optical beam path offers registration
and critical dimension (CD) metrology using transmitted or reflected light. The short wavelength together with an NA of
0.6 also allows sufficient resolution even at working distances compatible with the use of pellicles, hence enabling the
tool for qualification of final masks. The open concept together with the use of 193 nm wavelength enables a higher NA
for pellicle-free applications, including extreme ultraviolet (EUV) masks. This paper reports the current status of
PROVETM, highlighting its resolution capabilities while measuring production features as well as key registration
specifications.
Microelectronics industry leaders consistently cite the cost and cycle time of mask technology and mask supply as top critical issues. A survey was designed with input from semiconductor company mask technologists and merchant mask suppliers and support from SEMATECH to gather information about the mask industry as an objective assessment of its overall condition. This year's assessment was the eighth in the current series of annual reports. Its data were presented in detail at BACUS, and the detailed trend analysis is presented at EMLC. With continued industry support, the report can be used as a baseline to gain perspective on the technical and business status of the mask and microelectronics industries. The report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask industry. Its results will be used to guide future investments on critical path issues. This year's survey is basically the same as the surveys in 2005 through 2009. Questions are grouped into six categories: General Business Profile Information, Data Processing, Yields and Yield Loss Mechanisms, Delivery Times, Returns, and Services. Within each category is a multitude of questions that creates a detailed profile of both the business and technical status of the critical mask industry.
Microelectronics industry leaders routinely name the cost and cycle time of mask technology and mask supply as top
critical issues. A survey was created with support from SEMATECH and administered by David Powell Consulting
to gather information about the mask industry as an objective assessment of its overall condition. The survey is
designed with the input of semiconductor company mask technologists and merchant mask suppliers. This year's
assessment is the eighth in the current series of annual reports. With ongoing industry support, the report can be used
as a baseline to gain perspective on the technical and business status of the mask and microelectronics industries.
The report will continue to serve as a valuable reference to identify the strengths and opportunities of the mask
industry. The results will be used to guide future investments pertaining to critical path issues. This year's survey is
basically the same as the 2005 through 2008 surveys. Questions are grouped into categories: General Business
Profile Information, Data Processing, Yields and Yield Loss Mechanisms, Delivery Times, Returns, and Services.
Within each category is a multitude of questions that create a detailed profile of both the business and technical
status of the critical mask industry. This in combination with the past surveys represents a comprehensive view of
changes in the industry.
Microelectronics industry leaders routinely name the cost and cycle time of mask technology and mask supply as top
critical issues. A survey was created with support from SEMATECH to gather information about the mask industry as an
objective assessment of its overall condition. This year's survey data were presented in detail at BACUS and the detailed
trend analysis presented at EMLC. The survey is designed with the input of semiconductor company mask technologists
and merchant mask suppliers. This year's assessment is the seventh in the current series of annual reports. With
continued industry support, the report can be used as a baseline to gain perspective on the technical and business status
of the mask and microelectronics industries. The report will continue to serve as a valuable reference to identify the
strengths and opportunities of the mask industry. The results will be used to guide future investments on critical path
issues. This year's survey is basically the same as the surveys in 2005 through 2007. Questions are grouped into seven
categories: General Business Profile Information, Data Processing, Yields and Yield Loss, Mechanisms, Delivery Times,
Returns, and Services. (Examples are given below). Within each category is a multitude of questions that creates a
detailed profile of both the business and technical status of the critical mask industry.
The cost of ownership (CoO) of candidate technologies for 22 nm half-pitch lithography is calculated. To more accurately compare technologies with different numbers of process steps, a model that includes deposition, etching, metrology, and other costs is created. For 22 nm half-pitch nodes, extreme ultraviolet lithography (EUVL) has a significant cost advantage over other technologies under certain mask cost assumptions. Double patterning, however, may be competitive under worst-case EUVL mask cost assumptions. Sensitivity studies of EUVL CoO to throughput and uptime show EUVL may be cost-competitive at lower uptime and throughput conditions. Finally, calculation of the CoO of 450 mm lithography shows that the expected cost reduction is between 0% and 15%.
The cost of ownership (COO) of candidate technologies for 32 nm and 22 nm half-pitch lithography is calculated. To more accurately compare technologies with different numbers of process steps, a model that includes deposition, etching, metrology, and other costs is created. Results show lithography COO for leading edge layers will increase by roughly 50% from the 45 nm to the 32 nm half-pitch nodes. Double patterning and extreme ultraviolet lithography (EUVL) technologies have roughly the same COO under certain conditions. For 22 nm half-pitch nodes, EUVL has a significant cost advantage over other technologies under certain mask cost assumptions. Double patterning, however, may be competitive under worst case EUVL mask cost assumptions. Sensitivity studies of EUVL COO to throughput and uptime show EUVL may be cost-competitive at lower uptime and throughput conditions. In spite of these higher costs, total lithography costs for 32 nm and 22 nm half-pitches remain within reach of the Moore's Law trend. Finally, the COO of 450 mm lithography is calculated and shows the expected cost reduction is between 0% and 15%.
Microelectronics industry leaders routinely name the cost and cycle time of mask technology and mask supply as top
critical issues. A survey was created with support from SEMATECH and administered by David Powell Consulting
to gather information about the mask industry as an objective assessment of its overall condition. The survey is
designed with the input of semiconductor company mask technologists, merchant mask suppliers, and industry
equipment makers. This year's assessment is the seventh in the current series of annual reports. With ongoing
industry support, the report can be used as a baseline to gain perspective on the technical and business status of the
mask and microelectronics industries. The report will continue to serve as a valuable reference to identify the
strengths and opportunities of the mask industry. The results will be used to guide future investments pertaining to
critical path issues. This year's survey is basically the same as the 2005 through 2007 surveys. Questions are
grouped into categories: General Business Profile Information, Data Processing, Yields and Yield Loss Mechanisms,
Delivery Times, Returns, and Services. Within each category is a multitude of questions that create a detailed profile
of both the business and technical status of the critical mask industry.
Anticipating the cost of ownership (COO) of different lithography approaches into the future is an
act of faith. It requires that one believe that all of the lithographic problems with next generation lithography
(NGL) approaches will be sufficiently resolved to support the production of manufacturing wafers. This paper
assumes that all of the necessary technologies will be available in the future and that the cost of the
components can be extrapolated from historic cost trends. Mask and wafer costs of a single critical
lithography layer for the 65, 45, 32 and 22 nm half-pitch (HP) nodes will be compared for immersion, double
process (DP), double expose (DE), extreme ultraviolet (EUV), and imprint technologies. The mask COO
analysis assumes that the basic yield of an optical mask is constant from node to node and that the
infrastructure that allows this performance will be in place when the technologies are needed. The primary
differences in mask costs among lithography approaches are driven by the patterning write time and
materials. The wafer COO is driven by the mask cost (for the low wafer-per-mask use case), the lithography
tool cost, and the effective wafers per hour (wph) for the lithography approach being considered.
Extending lithography to 32 nm and 22 nm half pitch requires the introduction of new lithography technologies, such as
EUVL or high-index immersion, or new techniques, such as double patterning. All of these techniques introduce large
changes into the single exposure immersion lithography process as used for the 45 nm half pitch node. Therefore, cost
per wafer is a concern. In this paper, total patterning costs are estimated for the 32 nm and 22 nm half pitch nodes
through the application of cost-of-ownership models based on the tool, mask, and process costs. For all cases, the cost of
patterning at 32 nm half pitch for critical layers will be more expensive than in prior generations. Mask costs are
observed to be a significant component of lithography costs even up to a mask usage of 10,000 wafers/mask in most
cases. The more simple structure of EUVL masks reduces the mask cost component and results in EUVL being the most
cost-effective patterning solution under the assumptions of high throughput and good mask blank defect density.
Microelectronics industry leaders routinely name the cost and cycle time of mask technology and mask supply as top
critical issues. A survey was created with support from SEMATECH and administered by SEMI North America to
gather information about the mask industry as an objective assessment of its overall condition. This year's survey
data were presented in detail at BACUS and the detailed trend analysis presented at EMLC. The survey is designed
with the input of semiconductor company mask technologists, merchant mask suppliers, and industry equipment
makers. This year's assessment is the sixth in the current series of annual reports. With continued industry support,
the report can be used as a baseline to gain perspective on the technical and business status of the mask and
microelectronics industries. The report will continue to serve as a valuable reference to identify the strengths and
opportunities of the mask industry. The results will be used to guide future investments on critical path issues. This
year's survey is basically the same as the 2005 and 2006 surveys. Questions are grouped into eight categories:
General Business Profile Information, Data Processing, Yields and Yield Loss, Mechanisms, Delivery Times,
Returns and Services, Operating Cost Factors, and Equipment Utilization. Within each category is a multitude of
questions that creates a detailed profile of both the business and technical status of the critical mask industry. Note:
the questions covering operating cost factors and equipment utilization were added to the survey only in 2005;
therefore, meaningful trend analysis is not available.
Microelectronics industry leaders routinely name the cost and cycle time of mask technology and mask supply as top
critical issues. A survey was created with support from SEMATECH and administered by SEMI North America to
gather information about the mask industry as an objective assessment of its overall condition. The survey is
designed with the input of semiconductor company mask technologists, merchant mask suppliers, and industry
equipment makers. This year's assessment is the sixth in the current series of annual reports. With ongoing industry
support, the report can be used as a baseline to gain perspective on the technical and business status of the mask and
microelectronics industries. The report will continue to serve as a valuable reference to identify the strengths and
opportunities of the mask industry. The results will be used to guide future investments pertaining to critical path
issues. This year's survey is basically the same as the 2005 and 2006 surveys. Questions are grouped into categories:
General Business Profile Information, Data Processing, Yields and Yield Loss Mechanisms, Delivery Times,
Returns and Services, Operating Cost Factors, and Equipment Utilization. Within each category is a multitude of
questions that create a detailed profile of both the business and technical status of the critical mask industry.
Chromeless PSM photomasks have been successfully applied to a production memory application. This 248-nm application has allowed an extremely aggressive, dense design to be successfully deployed without changing wavelength. This was achieved with an advanced resolution enhancement technique, a chromeless phase-shifting mask, to provide a more cost-effective total lithographic solution. The key to this technology is a mask that delivers high wafer-die yields, while delivering resolution at low k1. Therefore, the mask must have zero printing defects. In order to understand printing defects, many types of potential defects were analyzed and correlated back to the mask locations using both a 248-nm AIMs tool and SEM images. These defects were also correlated to a 257-nm KLA 576 tool using die-to-die inspection runs. This paper will examine chromeless mask phase-defect printing effects by using inspection capture at the key manufacturing steps (post-Cr etch, post-Qz Etch, and post-Cr removal). These defects will then be tracked through processes using SEM, AIMs, RAVE repair, and post-repair AIMs.
At SPIE Microlithography 2005, the concept of direct imprinting of dielectric material for dual damascene processing and its benefits was introduced 1. Manufacturing a nano-imprint template with multi-tier 3-D structures presents a unique set of challenges. The main issues are patterning two different mask layers with good overlay and etch depth control into the quartz at each step on the same substrate. This work describes the tools and processes used to build these types of structures in a commercial photomask shop. The results of using a template with two levels of patterning to imprint dual damascene 3-D structures will also be presented.
CPL and aerial image mapping type contact designs for both negative and positive tones were created, built and tested for 100 nm and sub-100 nm contacts. Experimental results illustrated the need for electromagnetic-field corrections in the simulations. Resolution down to 80nm dense contacts were seen with both negative and positive resists with acceptable process windows though some process optimization is still required as unacceptable CD variation and a reentrant profile was observed. High MEEF requires strict CD control on the mask. Data volume for the isolated contact designs can also challenge the mask build.
Lithography costs for IC production at resolutions of 65-nm and beyond have grown exponentially for each technology node and show no sign of slowing. Step and Flash Imprint Lithography (S-FIL), developed at the University of Texas (UT) uniquely offers IC manufacturers the potential for lower cost of ownership, because S-FIL does not require expensive optics, advanced illumination sources or chemically amplified resists (CAR). The SIA’s addition of Imprint Lithography to the International Technology Roadmap for Semiconductors (ITRS) in 2003, indicates the promise to become a preferred technology and has some compelling advantages over traditional 4X optical lithography.
Advanced 90nm binary & phase shift mask processes have been altered using thin Cr (15-nm) & thin e-beam resist (<150nm) resulting in sub 100-nm geometries necessary for S-FIL, and have become the baseline for template manufacture. Commercial production of advanced 1X templates requires CD metrology capability beyond the equipment typically used in 4X mask making. Full commercialization of Imprint Lithography requires not only the ability to generate a 1X template but also a metrology solution that can characterize critical dimension (CD) parameters of the template. Previous published work on S-FIL has focused mainly on high resolution templates produced on 100keV Gaussian pattern generators (PG), and has shown that resolution is only limited by the template.
This work demonstrates that an advanced commercial photomask facility can fabricate templates with sub-100 nm critical dimensions, and that the CDs can be characterized using a commercially available CD-SEM metrology tool. CD metrology repeatability of 0.7nm 3σ was established on a quartz only template with a 6025 form factor.
A NIST traceable phase1 shift standard has been designed, fabricated, and tested on three phase shift measurement tools using different wavelengths. By using the fundamentals of NIST traceable step height, quartz index, and the understanding of the illumination optics of the Lasertec phase metrology tool, a phase standard has been created which can be used to calibrate Lasertec phase metrology tools. The pattern that is used is compatible with the recommended best practices for calibrating and measuring step heights and phase on the Lasertec tools. The mask is made with multiple depths. The three mask depths allow for the mask to be calibrated to three NIST traceable depth heights. This was done using the FEI SNP XT depth metrology tool. Since the mask format is mask based (6x250 Cr on quartz), it can be easily used on mask manufacturing metrology systems. The depths are targeted at the 180-degree phase shift for 157nm, 193nm, and 248nm lithography. The mask can be used to set targets and check the linearity of the phase metrology tools. The patterns are compatible with AFM and Profilometer depth metrology tools as well as multiple Lasertec spot sizes and shearing distances. The quartz depths are fabricated using a wet quartz etch process. The wet etch minimizes the quartz roughness and removes that error source from the metrology. The pattern is also arrayed so that multiple sites can be used to confirm the metrology and the prime measurement site could be changed if there was a suspicion of pattern damage or contamination.
As the semiconductor-process technology advances towards the 90nm-node, more and more wafer-fabs start to use 193nm EAPSM (Embedded Attenuated Phase-Shift Mask) technology as the main lithography strategy for the most critical-layers. Because the 193nm EAPSM is a relative new technology in the semiconductor industry, it is important for us to understand the key-mask-specifications in a 193nm EAPSM and their impact to the wafer process windows. In this paper, we studied the effects of phase-angle and transmission to the wafer process window of a 193nm-EAPSM in a 300mm wafer-manufacturing environment. We first fabricated a special multi-phase EAPSM by a combination of extra Quartz-etch and Mosi-removal. We then used a high NA 193nm scanner (ASML-ALTA1100) and high contrast resist to perform the wafer-level printing study. To fully understand the impact of phase-angle and transmission to wafer process windows, we also used AIMS (Aerial-Image Measurement System) and Prolith simulation software to study the lithographic performances of various phase-angle and transmission combinations. By combining the wafer-level resist imaging printing results, AIMS studies and Prolith-2 lithography simulations, we proposed the practical phase-angle and transmission specifications for the 90nm-node wafer process.
AAPSM masks require OPC correction through pitch in order to print a linear dark line response vs the design CDs. The masks also require correction for the clear intensity imbalance caused by the phased etched Qz wall edge. The clear intensity can be balanced by two approaches;(or a combination of the two) data biasing or wet undercut etching of the Qz etched opening. IC manufacturers would like to use one OPC model that will work for any mask fabrication approach. This paper shows that there is no OPC difference observed in either the aerial image or the printed image of several OPC learning patterns. The study includes CD through pitch for dense (1:1) L/S Patterns and Isolated Line CD vs line-space ratio. The images were analyzed for the dark line linearity, the clear CD balance though pitch, and the clear CD balance with focus (phase error effects -PES).
Production readiness of phase-edge/chromeless reticles employing off-axis illuminations for 65nm node lithography is assessed through evaluation of mask design conversion and critical layer lithography performance. Using ASML /1100ArF scanners, we achieved k1=0.33 for chromeless phase shift mask (crlPSM) with more than 0.6um DOF for dense features. Subresolution assist features allow for acceptable depth of focus through pitch. However, chromeless feature linearity fall-off continues to be a major issue hampering the acceptance of crlPSM for production. Several mask data conversion schemes such as chromeless gratings and chrome patches have been proposed as viable solutions to mitigate the chromeless linearity fall-off issue. We evaluated chromeless gratings, chromeless rims and chrome patches and report on their performance in resolving the chromeless linearity fall-off issues as well as mask process complexity associated with each solution.
An investigation of the predominant industry approaches to transmission balance and phase error through pitch of Alternating Aperture Phase-Shifting Mask manufacturing approaches has been conducted. Previous theoretical studies have shown both clear pattern bias and phase error changes through pitch. These variations are significant for the Low K1 applications. Several approaches have been proposed and discussed in previous papers, including undercut, asymmetric pattern biasing, mask phase-only, dual trench, SCAA, and others. Although much of the discussion has focused on lithographic process performance, some of the constraints in the mask making infrastructure may differentiate between processes of similar performance. Two manufacturable approaches, wet etch undercut and asymmetric pattern biasing, have been studied by electromagnetic field simulation to explore the across pitch performance at 193nm. This has been compared to experimental measurement of photomasks measured with a 193 Zeiss AIMS (Aerial Image Microscope System). Both mask fabrication approaches are compared to the simulations. The performance of both mask approaches to pattern bias and phase error was evaluated, and the feasibility of through pitch correction and its impact on design and manufacturability of the photomask is discussed.
For logic design, Chrome-less Phase Shift Mask is one of the possible solutions for defining small geometry with low MEF (mask enhancement factor) for the 65nm node. There have been lots of dedicated studies on the PCO (Phase Chrome Off-axis) mask technology and several design approaches have been proposed including grating background, chrome patches (or chrome shield) for applying PCO on line/space and contact pattern. In this paper, we studied the feasibility of grating design for line and contact pattern. The design of the grating pattern was provided from the EM simulation software (TEMPEST) and the aerial image simulation software. AIMS measurements with high NA annular illumination were done. Resist images were taken on designed pattern in different focus. Simulations, AIMS are compared to verify the consistency of the process with wafer printed performance.
The focus of this paper is on the development and implementation of a correction strategy that enables mask manufacturers to maintain the yields at current levels while simultaneously reducing registration errors by several nanometers. An alternate consequence is that yields at current registration specifications are improved. Previous work has shown that one source of image placement error is the chrome stress relief caused by etching. This can cause over 25 nm of distortion from the resist pattern to the final etched chrome pattern. Theoretical and experimental data have shown that the distortion has a radial signature, which can be significantly reduced by traditional magnification correction. If the magnitude of this correction term can be predicted before patterning, the magnification can be implemented as a correction term in the writing process, minimizing registration errors. Studies have shown that the percent clear area of the mask, x-field size, y-field size, and chrome stress are the key parameters that will affect the correction term. Data based on finite element simulations were first fit to these parameters to obtain a predictive curve based upon theory. Experimental reticles were then written to test the theoretical prediction. The predictions were found to coincide well with the experimental data; registration improvements of over 20 nm were observed. The correlation was then applied to a set of production reticles. There was an observable improvement in registration after the correlation was implemented, although less than that seen in the experimental reticles.
Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/-9nm. Defectivity levels must also be below one failure per billion contacts for acceptable device yield. Difficulties in contact patterning are driven by the low depth of focus of isolated contacts and/or the high mask error (MEF) for dense contact arrays (in combination with expected reticle CD errors). Traditional contact lithography methods are not able to mitigate both these difficulties simultaneously. Inlaid metal trench patterning for the 65nm generation has similar lithographic difficulties though not to the extreme degree as seen with contacts. This study included the use of multiple, high transmission, 193nm attenuated phase shifting mask varieties to meet the difficult challenges of 65nm contact and trench lithography. Numerous illumination schemes, mask biasing, optical proximity correction (OPC), mask manufacturing techniques, and mask blank substrate materials were investigated. The analysis criteria included depth of focus, exposure latitude and MEF through pitch, reticle inspection, reticle manufacturability, and cost of ownership. The investigation determined that certain high transmission reticle schemes are strong contenders for 65nm generation contact and trench patterning. However, a number of strong interactions between illumination, OPC, and reticle manufacturing issues need to be considered.
Semiconductor manufacturers are increasingly focusing on contact and via layers as the most difficult lithography pattern. Focus and exposure latitude, MEF, as well as iso-dense bias are challenges for contact patterning. This situation is only expected to worsen for the 65nm device generation where the 2001 SIA roadmap update lists the contact size as 90-100nm in 2004-2005. Thus, new contact pattern techniques with novel manufacturability are required. One possible avenue to meet these stringent process control requirements is the use of tri-tone high transmission attenuated phase shifting masks (tri-tone AttPSM) for the 65nm generation.
Multilayered SiN/TiN (9%-18%) EAPSM materials to manufacture advanced reticles were used in this investigation. Extensive study during the photomask processing (Front End and Back End) to access any issues related to the making of High %T tri-tone product types was performed.
Finally, the 2 prototype reticles were evaluated on a 193nm scanner (0.75NA) with various illumination settings to generate imaging to support the 65nm node technology generation.
Alternating aperture phase shifting mask (AAPSM) technology is finding increased use in the patterning of critical layers due to the enhanced resolution and decreased linewidth variation characteristic of this technique. The potential advantages of AAPSM processes must be weighed against the increased complexity of reticle layout, higher reticle cost, and heightened sensitivity to parameters such as lens aberration. This work details the effect of shifter trench depth on patterning performance for the 100nm node. Data was collected at an exposure wavelength of 193nm using reticles built with deliberate errors in shifter trench depth. Differences in patterning performance observed as a result of these variations are compared with the impact predicted from modeling.
Aberrations, aberrations, here there everywhere but how do we collect useful data that can be incorporated into our simulators? Over the past year there have no less than 18 papers published in the literature discussing how to measure aberrations to answering the question if Zernikes are really enough. The ability to accurately measure a Zernike coefficient in a timely cost effective manner can be priceless to device manufacturers. Exposure tool and lens manufacturers are reluctant to provide this information for a host of reasons, however, device manufacturers can use this data to better utilize each tool depending on the level and the type of semiconductors they produce. Dirksen et al. first discussed the ring test as an effective method of determining lens aberrations in a step and repeat system, later in a scanning system. The method is based on two elements; the linear response to the ring test to aberrations and the use of multiple imaging conditions. The authors have been working to further enhance the capability on the test on the first small field 157 nm exposure system at International SEMATECH. This data was generated and analyzed through previously discussed methods for Z5 through Z25 and correlated back to PMI data. Since no 157nm interferemetric systems exist the lens system PMI data was collected at 248nm. Correlation studies have isolated the possible existence of birefringence in the lens systems via the 3-foil aberration which was not seen at 248nm. Imaging experiments have been conducted for various geometry's and structures for critical dimensions ranging from 0.13micrometers down to 0.10micrometers with binary and 0.07micrometers with alternating phase shift mask. The authors will review the results of these experiments and the correlation to imaging data and PMI data.
Repair and printability of 193nm alternating aperture phase shift masks have been studied in detail in an effort to understand the overall production capability of these masks for wafer production at the 100nm node and below.
Binary halftone chromeless PSM (CLM) can be described as a 100% transmission attenuated PSM (attPSM). The term 'binary halftone' refers to a novel OPC application to achieve the necessary CD control across the full feature-pitch range. We find that CLM is very complimentary -- with high numerical aperture (NA) and with off-axis illumination (OAI). In our wafer-printing experiment, we have achieved 70 nm through- pitch printing performance, using a KrF resist process. This was done in combination with a rule-based SB-OPC approach. At least 0.4 micrometer overlapped DOF with more than 6% exposure latitude has been attained for sub-100 nm printed features. For 2D complex patterns, we have observed a very strong optical proximity effect. CLM appears to be more sensitive to proximity effects, but less sensitive to lens aberration effects. Further experimentation and verification is required. Current mask-making processes appear to be capable of manufacturing CLM. We conclude that CLM has great potential to achieving production-worthy (lambda) /4 (or 0.2k1) lithography. The technology risk is neither in mask making nor in application software, but may be in reticle inspection and repair.
For lithography smaller that 180 nm using 248 nm steppers, phase-shifting lithography is becoming more routine. However, when applied to very small dimensions, OPC effects begin to become pronounced. We have design a new phase- shifting test structure for reticles to address these phase shifting distortions, and report on its use.
Optical lithography is one of the key enabling technologies in semiconductor microcircuit fabrication. As the demand for devices with higher performance and speed continue, the need for patterning circuits with finer features is driving optical microlithography to shorter and shorter wavelengths (248 nm yields 193 nm yields 157 nm). This is because the resolution with traditional Cr masks, that either block or pass light for imaging, is limited by optical diffraction. At any wavelength, however, phase-shift masks can enhance resolution beyond the wavelength-imposed diffraction limit. Phase-shift masks work by employing destructive optical interference to enhance contrast. This paper discusses a novel, systematic materials approach--optical superlattices- -to design embedded attenuating phase-shift masks, the most versatile and common type phase-shift mask, for any optical wavelength. These superlattices are comprised of alternating, ultrathin (< 10 nm) layers of an optically transparent compound multilayered with an optically absorbing one, e.g., Si3N4 and TiN. Film structure, optical properties, etching, chemical stability, and radiation durability are discussed.
We have developed a new attenuating embedded phase-shift mask blank for 193 nm lithography based on novel TiSi-nitride chemistry. At 193 nm, these materials offer high optical transmission, they are radiation damage resistant, stable in common chemicals used to strip photoresist, process compatible with use of a hard Cr etch mask, and exhibit good dry etch selectivity to quartz. Specifically, optical transmissions of greater than 10% were achieved in films with 180 degree phase- shift. Irradiation at 6 mJ/cm2/pulse, or approximately 60x the energy densities in commercial steppers, caused small change in optical transmission for doses up to 2 kJ/cm2. Dry etching the films in an ICP reactor with CF4 gave a greater than 6:1 etch selectivity to quartz. Further, the novel wavelength-tunable structure of these TiSi-nitride films permits equally attractive phase-shift designs at 248 nm and longer wavelengths.
In this paper we present results of an algorithm that has been developed which is sensitive to phase defects of 60 degrees on i-line alternating PSMs. This algorithm consists of microcode and software, which can be loaded into existing inspection hardware. The algorithm works in die-to-die inspection mode and uses both transmitted and reflected light images to maximize sensitivity. Isolated phase defects as well as phase defects close to chrome edges were inspected. In addition, the algorithm is able to detect missing and mis-aligned shifter edges. A programmed phase defect test plate was developed to characterize defect detection sensitivity. Detection of 60 degrees defects smaller than 0.75 micrometers has been demonstrated with this algorithm. Defect sensitivity characterization and actual production plate effect results are shown. Finally, recent results showing the application of the algorithm to the inspection of Deep-UV multiphase reticles using a shorter inspection wavelength are presented.
In this paper we present results of an algorithm that has been developed which is sensitive to phase defects of 60 degrees on i-line alternating PSMs. This algorithm consists of microcode and software which can be loaded into existing inspection hardware. The algorithm works in die-to-die inspection mode and uses both transmitted and reflected light images to maximize sensitivity. Isolated phase defects missing and misaligned shifter edges. A programmed phase defect test plate was developed to characterize defect detection sensitivity. Detection of 60 degree defects smaller than 0.75 micrometer has been demonstrated with this algorithm. Defect sensitivity characterization and actual production plate defect results are shown.
The manufacture of an embedded attenuating phase shift mask (E-APSM) is the simplest among all the phase shift mask (PSM) types. This is because an E-APSM provides the necessary attenuation and phase shift requirements using a single layer absorber film. Therefore, the tasks of patterning, inspection and repair are much easier to accomplish than for a multi-level quartz etched or SOG/SiO2 coated PSM. Reports in literature indicate that an E-APSM, also referred to as a single-layer half-tone PSM, is likely to be used for the contact masking layer in the manufacture of 64 M-bit DRAMs. It has also been stated that defect-free E-APSMs will be manufactured using currently available mask making tools. Therefore, it could be inferred that the defect specifications for an E-APSM are expected to be the same as that for a standard chrome mask. Perturbation modeling studies indicate that this should be true. An experimental study of repair and printability of defects on contacts on an E- APSM, using a chrome-based embedded attenuating film was performed. Exposures were made on an i-line stepper with NA equals 0.6 and sigma equals 0.6. Oxide wafers were coated with a high contrast i-line resist and the contact pattern was transferred into the oxide using a decorative etch process. Measurements were made using a SEM. The wafer results were also compared with printability studies done using an aerial imaging measurement system. The results of repairs done on 1 micrometer size defects on 2 micrometer size contacts indicate that the currently available laser repair tool was successful in restoring the lithographic performance of the E-APSM contacts to an acceptable level.
Attenuated embedded phase shifting photomask technology can improve lithography performance for both g-line and i-line steppers. Emphasis at i-line is shifting from development to production as lithographers integrate phase shifting masks into their processes. This paper describes pilot production of i-line and g-line, Cr-based, attenuated embedded phase shifter photoblanks and photomasks.
I-line (365 nm) and G-line (436 nm) attenuated phase shifting photomasks have been developed using single layer Cr-based photoblanks. The absorber layer has a composition gradient that allows the desired transmission to be tuned while maintaining control over reflectivity and phase shift. These photoblanks are manufactured in existing facilities, and masks are processed much like conventional opaque Cr-based materials. They can be inspected and repaired on current equipment with slight modifications. Printing has been demonstrated on current generation steppers. Deep UV extendability of these materials is also being studied, with a 5% Deep UV (248 nm) single layer photoblank chemistry already demonstrated.
Issues associated with the commercialization of phase shift masks are discussed. Design layouts incorporating multiphase transitions and voting are presented along with methods of mask fabrication. Issues associated with mask inspection and repair are discussed, along with data on actual reticles produced using the prescribed method of manufacture. Cost of reticles in relation to potential wafer processing gains are compared along with problems associated with the increased complexity of the mask making process.
A 25 key focused Ga ion beam was used to induce deposition
of tungsten on a gold absorber on boron nitride X-ray mask with
submicron features to simulate the repair of clear defects.
Tungsten was deposited to fill holes, extend lines and add
missing features, such as isolated contacts and lines. Deposits
were placed between features and made to cross over both gold
and tungsten features to evaluate proximity effects. Series of
tungsten depositions that varied in thickness were exposed to an
X-ray source and transferred into resist. Contrast equivalent
to or better than the gold absorber was achieved for tungsten
that was thinner than the gold.
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