This PDF file contains the front matter associated with SPIE Proceedings Volume 12499, including the Title Page, Copyright information, Table of Contents, and Conference Committee information.

This invited talk describes the enabling process technologies for advanced logic devices beyond FinFET era. Gate-all-around (GAA) improves electrostatics over FinFET and enables continuous gate length scaling. Complementary FET (CFET), which is a structure of stacked transistors, is a next candidate architecture for the continuous cell height scaling enablement. Interconnect pitch scaling will also play crucial role for it and go with RC reduction knobs such as Cu damascene extension, post Cu and airgap. For better area usage and performance enhancement, backside power delivery network (PDN) is an attractive option. For these enablement, continuous process and tool advancement is necessary not only on film, etch, lithography and wet, but also on wafer bonding and thinning technologies. We will also review our recent progress in EUV related solutions including self-aligned patterning.

Semiconductor process development for state-of-the-art devices is a complex task that requires up to years of development. The complexity comes from the need to tune a significant number of process knobs in latest process tools, to meet multiple on-wafer performance targets, across an entire wafer. AppliedPRO^® is a software and library of algorithms developed by Applied Materials for process recipe optimization to meet simultaneous process requirements across the entire wafer. The software is tailored to semiconductor use-cases and designed to be primarily used by process engineers to make critical decisions with confidence during process development. Over 100 use-cases have been generated for various semiconductor chips manufacturers, showing faster development time, less development resources, and higher process engineer productivity. This paper shows the use-case of Samsung N+1 Logic BEOL Spacer-Etch process recipe optimization using AppliedPRO^®. We utilized AppliedPRO^® structured design of experiment methodology and machine-learning algorithms to simultaneously model 10 process-recipe knobs of Applied Materials’ Centris^® Sym3^® X Etch system and their effect on 8 on-wafer metrics, and determine optimal process knob conditions for minimizing Spacer-tail, which is a key performance metric, while keeping other metrics close to spec. These optimized conditions reduced Spacer-tail by 73% on coupons, which was also validated on full-wafer. These optimal results were previously unachievable in all the previous experimental trials before introducing AppliedPRO^®.

The impact of both intrinsic and plasma-induced stress of a TiN hardmask on line wiggling was investigated via etching of p-SiOCH with 28 nm pitch, line and space (L/S) EUV resist patterning. Experimental stacks included crystalline PVD TiN with an intrinsic stress of +0.1 GPa and several PEALD TiN films with varying crystallinity and intrinsic stresses ranging from -3.6 GPa (compressive) to +0.2 GPa (tensile). Results confirmed that reduction of intrinsic TiN stress can prevent wiggling¹ when the mask is not exposed to plasma during process flow. However, when TiN is exposed to plasma as in a typical back end of line (BEOL) process^2-3, compressive stress increased in all films and resulted in wiggling even in the patterned PVD TiN sample with low intrinsic stress. This global increase in compressive stress due to plasma exposure did not correlate with intrinsic stress values, therefore, this work suggests a greater focus should be placed on plasma-induced stress to avoid line wiggling when selecting a TiN film. Further investigation found that increased surface roughness of the TiN mask can decrease the risk of wiggling, and that surface roughness is influenced by p-SiOCH etch selectivity, indicating mask surface roughness should also be considered when evaluating line wiggling in BEOL, p-SiOCH etching.

In today’s advanced semiconductor process manufacturing, critical dimensions of device features have decreased to a few nanometers while the aspect ratios have increased beyond 100. The cost of process development has significantly increased and the performance of the lithography and plasma etch patterning processes are critical to the success of ramping a new technology node toward profitable high-volume manufacturing. In this paper, a three-dimensional Monte Carlo-based feature scale model, ProETCH^®, has been developed for modeling etch process with the capability of optimizing the process by solving forward and inverse problems. The shallow trench isolation etch process in self-aligned double patterning was investigated. The mechanism of silicon etch by Ar/Cl2 plasma was developed with experimental data as a reference. The developed model captures the trends and has quantitative accuracy in comparison to the experimental data, and can be used to identify the different fundamental pathways which contribute to the profile metrics. The developed model was then used to solve the forward problem, which is to predict profiles at different process conditions, and the inverse problem, which is to search for the process conditions (e.g, power and pressure) which could result in desirable profiles.

The etch profile control for the amorphous carbon layer (ACL) is an important step in the 3D NAND fabrication process. Because ACL is the mask material for defining the pattern of the high-aspect-ratio-contact (HARC) dielectric ONON layer etch process, precise control of its etch profile is necessary. Specifically, an ideal ACL mask profile should be free of symptoms such as hole circularity distortion, profile twisting, bowing, and undercutting. In order to achieve this desired etch performance, knowledge of various etch contributing factors must be systematically derived and applied, including etch surface chemistry, high-aspect-ratio (HAR) etchant transport, ion flux and ion energy angle distribution function (EADF) control, etc. In this work, we investigate the ACL etch fundamental characteristics through combined 2D chamber-scale plasma simulations with the hybrid plasma-equipment model (HPEM) and 3D etch profile simulations with the Monte-Carlo Feature Profile Model (MCFPM) for an inductively-coupled-plasma (ICP) reactor with RF bias at the substrate. In particular, we focus on the profile trends under different reactant fluxes and energies. Our findings indicate that maintaining a neutral-starved (ion-rich) etch regime is essential for mitigating both the channel hole etch circularity distortion and the slit etch profile twisting. To achieve this desired etch regime, the HAR ion, and neutral transport must controlled by the RF bias power and frequency, substrate temperature, etc. Furthermore, especially in this neutral-limited etch regime which is necessary for distortion and twisting mitigation, the control of the consequent aspect-ratio dependent etching (ARDE), as well as maintaining the critical dimension (CD) and reducing bowing and undercutting are also necessary. For this purpose, atomistic density functional theory (DFT) calculations have been applied to compare the reaction energetics for various ALD-like sidewall passivation chemistries. Specifically, we propose a new process based on its favorable reaction energetics. Experimental cross-section images have matched simulation results. In conclusion, our insights have provided guidance for process optimization and tool design to meet industrial demands.

Reducing process development time and speeding up time to market are perennial challenges in the microelectronics industry. The development of etch models that permit optimizations across the wafer would enable manufacturers to optimize process design flows and predict process defects before a single wafer is run. The challenges of across-wafer uniformity optimizations include the large variety of features across the wafer, etch variations that occur at multiple scales within the plasma chamber, feature metrology, and computationally expensive model development. Compounding these challenges are trade-offs between data quality and time/cost-effectiveness, the wide variety of measurement information provided by different tools, and the sparsity and inconsistency of human-collected data. We address these challenges with a feature and wafer level modeling approach. First, experiments are conducted for a variety of etch conditions (e.g., pressure, gas composition, flow rate, temperature, power, and bias). Second, a feature level model is calibrated at multiple sites across the wafer based on OCD and/or cross-sectional SEM measurements. Finally, the calibrated model is used to predict an optimal set of process conditions to preserve uniformity across the wafer and to meet recipe targets. We demonstrate the methodology using SandBox Studio™ AI for a FinFET application. Specifically, we show the rapid and automated calibration of feature level models using experimental measurements of the 3D feature etch at a variety of process conditions. Automated image segmentation of X-SEM data is also performed here for single case using Weave^® to demonstrate how such data can be acquired quickly in a development environment. We then demonstrate the effectiveness of the reduced-order model to predict optimal recipe conditions to improve overall recipe performance. We show how, with this hybrid-metrology computational approach, a process window that yields 89.2% of the wafer can be captured.

In a complementary-FET (CFET), n- and p- type transistors are stacked on top of each other. This stacking approach results in very high aspect ratio vertical features which brings critical challenges for nanosheet (NSH), gate, spacer, and source/drain (S/D) cavity patterning. Silicon nitride spacers are commonly used to electrically isolate and protect the silicon gate during S/D epitaxial growth and to precisely define the channel length (Lg) [1-4]. In this work, we will discuss the spacer film opening, the optimization of the S/D cavity profile and propose options to reduce the gate hard mask consumption. We were able to straighten the S/D cavity profile in the SiGe superlattice substrate by tuning specific process parameters, during the various etch and over-etch steps of the stack. Chemical analysis of the sidewall of the cavity, by TEM/EDS, confirmed that the formation of a passivation oxi-nitride compound is key to achieve vertical cavity profile. The chemical mapping of the cavity was done through the Si and SiGe25% sheets. A Si, O and N containing passivation layer is present in the cavity which seems to be thicker at the top and thinner at the bottom of the cavity. Furthermore, polymer capping methods were investigated to reduce the consumption of oxide hard mask (HM) during spacer etch. Process optimization for the cavity shape in the S/D recess etch was conducted using TEM characterization.

In this paper, middle-of-line (MOL) plasma etch development results for the monolithic CFET integration with nanosheet devices using scaling-relevant test vehicle (CPP48nm) are presented. Several critical MOL patterning steps are addressed, with the focus on the patterning of the trenches (M0) for contacting to the bottom and top devices. The patterning of M0A consists of SiO₂ dielectric and thin SiN liner etch landing on epitaxial source drain (S/D). The critical M0 etch requirement is preserving the SiN gate spacer to avoid shorting between S/D and gate. Due to no-gate plug implementation in the process flow, the etch development must rely on very challenging, patterning the small critical dimension (CD) contacts to create enough dielectric barrier between the metal contact and the gate, and preferably, also very challenging, self-alignment to the thin gate spacer. The dependance of the M0 CD and the etch depth is accessed by using the range of the EUV lithography conditions and evaluating the maximum etch depth of the trench as a function of the printed CD. The minimum trench CD achieved on the bottom of the trench is ~ 13nm, and the minimum top CD in the range of ~ 16nm, with the evident etch non-uniformity observed in the etch depth. The trend of larger contact CD resulting in the deeper etch and process uniformity improvement is observed. Etch depth larger than 100nm is achieved when top M0 CD is >20nm. The option with the SiN liner deposition followed by SiN liner etch (spacer formation) post- M0 SiO₂ is developed. This patterning sequence consists of SiO₂ etch stopping on the thin SiN (over S/D) followed by additional SiN deposition and finally etching of the deposited SiN liner as well as SiN liner covering S/D. The option with SiN spacer formation minimizes the risk of short to the gate, due to extra SiN dielectric film protecting the gate. In addition, we present the results for another critical MOL patterning step, i.e., HAR metal recess post M0 metallization (AR~11)

With the introduction of Augmented Reality, Virtual Reality, and Mixed Reality (AR/VR/MR) applications, the fabrication of photonics devices is approaching a high volume manufacturing level. To scale these products to consumer friendly dimensions, there is still significant shrink needed for many not yet available components such as ultrasmall cameras, metalenses, microdisplays, and combiner optics. AR/VR/MR optical components include metalenses patterned over large areas, and the fidelity of these patterns may have a significant impact on performance. In this study, we apply OPC to the design intent and examine the implication of various lithographic and correction techniques on metalens performance through simulation. In addition, we investigate the root causes of the manufacturing process variability and its impact on metalens functionality. These devices are analyzed by comparing light propagation through the simulated manufactured system using rigorous lithographic models to the optimal system based on the design intent. The study finds that the size and shape of meta-atoms have a different impact on optical performance, depending on the type of the metalens.

In this work, process modeling was coupled with actual Si data to perform process optimization and control of an 18nm metal pitch (MP18) semi-damascene flow with fully self-aligned vias (FSAV). We explored the impact of process variations and patterning sensitivities on line and via resistances as well as on line capacitance variability. We also benchmarked capacitance variability using partial-airgap and gap fill options. From this study, we have identified significant process parameters and corresponding process windows that need to be controlled to ensure successful manufacturability of the MP18 semi-damascene flow.

Patterning, a major process in semiconductor manufacturing, aims to transfer the design layout to the wafer. Accordingly, the "process proximity correction" method was developed to overcome the difference in after-cleaninginspected CD (critical dimension) between patterns of similar shapes. However, its physical model is often limited in the predictive performance. Therefore, recent studies have introduced ML (machine learning) technology to supplement model accuracy, but this approach often has an inherent risk of overfitting depending on the type of sampled pattern. In this study, we present a newly invented flow capable of stable etch-process-aware ML modeling by model reconstruction and large amounts of measurement data. The new modeling flow can also be performed within a reasonable runtime through efficient feature extraction. Based on the new model and its related layout targeting platform, intensive improvements were made to CD targeting and spread; for a given layout, in comparison with delicate rule-based modification, the CD targeting accuracy was improved by 4 times and approaches the limit of metrology error.

With Moore’s law continues to drive IC feature size and device density, advanced technology evolves to enable not only smaller feature size but also 3D structures for logic and memory chipmakers.1 The associated process requires precise surface/interface functionality and material loss control, as a result plasma damage free process and isotropic etch with high selectivity became crucial for advanced 3D transistor manufacturing. High density radical based processes provide ideal solutions with very low electron temperature, excellent step coverage and ultra-high selectivity. The highly reactive radicals can largely reduce thermal budget as well. In this article radical based surface treatments and material modifications including metal treatment, surface reduction and surface smoothing are discussed. Furthermore, the benefits of combining such surface treatment and radical based selective etch are also presented with examples of Si and TiN etch processes. Both surface treatment and selective etch processes are enabled by high density ICP plasmas generated radicals.

There has been considerable interest in the development of isotropic atomic layer etching (ALE) for the conformal removal of thin films. Material selectivity is crucial for the development of isotropic ALE because the next generation of semiconductor devices will be constructed with miniaturized 3D structures using a variety of very thin films. We developed plasma-assisted thermal-cyclic ALE, which is a repetition of surface modification by plasma exposure and removal of the modified surface by infrared heating. We developed a 300-mm tool, namely, dry chemical removal (DCR), which is equipped with an inductively coupled plasma (ICP) source and infrared lamps, to facilitate rapid thermal desorption of the modified surface. An important feature of the plasma-assisted thermal-cyclic ALE is that it has more tuning knobs than that of conventional ALE because it uses two temperatures: a low temperature for surface modification and an elevated temperature for the removal of the modified surface. This paper presents the selective ALE of various materials, i.e., Si₃N₄, TiN, W, and SiGe using the developed tool. The mechanisms of the selectivity are divided into two categories: formation of an ammonium salt-based modified layer and selectivity control by adjusting the infrared heating time. This paper reviews the selective ALE mechanisms, focusing on the results of in situ analysis of surface reactions, and presents some of the latest findings.

Sustainability is gaining momentum as countries and companies announce targets for net-zero carbon emissions by 2050. imec has created a bottom-up model using tool data, process recipes, and integrated wafer process flows to create a virtual fab. With this model, it is possible to quantify the environmental impact of manufacturing integrated circuit (IC) chips for current and future logic and memory technology modes. In this paper, the model is used to identify areas with the highest environmental impact. It is important to reduce the impact of both lithography and etch since together they are responsible for 45% of total CO₂ equivalent emissions associated with fabricating an N3 logic node wafer. For lithography, two approaches to reducing the environmental impact will be described: one concentrates on tool consumption and the other on process choices to maximize throughput. For etch, the focus is on reducing overall gas consumption and improving wafer material stacks to minimize fluorocarbon use. Translating patterning process changes into emission numbers will enable informed process choices for future and contribute to a shift towards net-zero semiconductor manufacturing.

Fluorinated species are ubiquitous in semiconductor manufacturing, yet are known to have global warming potentials thousands of times higher than CO₂. As abatement technologies are not completely effective and add additional costs, interest in reducing these emissions increases with semiconductor manufacturing volumes. We explore alternative chemistries for common plasma etch applications that retain patterning performance but with near zero GWP. Spectroscopic identification and quantification of etch byproducts is presented to demonstrate the beneficial environmental impacts of transitioning from the most common etch gasses.

The recent passing of the CHIPS act has highlighted the semiconductor industry as a driver of innovation. Simultaneously, environmental legislation regarding per- and polyfluoroalkylated substances (PFAS) usage has become a major focus in both the US and EU, which has potential implications for many hydro- and perfluorocarbon (HFC/PFC) gases currently used in semiconductor manufacturing. High-aspect ratio (HAR) etch processes are a critical component of two high-growth manufacturing areas (packaging and solid-state memory), however, they are significant consumers of HFC/PFC chemistries due to the vertical scale of the features involved. This paper analyzes reduced gas flow effects in a HAR through-silicon via (TSV) etch process, with the aim of improving the sustainability of future processes through an improved mechanistic understanding. We demonstrate a cyclic C4F8 /SF6 TSV process with ~90% ER and comparable sidewall roughness using 50% of the SF6 flow rate and 60% of the passivation time. We also show through TOF-SIMS analysis a depth dependence of the sulfur and fluorocarbon concentrations on the TSV sidewall which varies with gas flow rate, providing further insight into the mechanisms associated with HAR etching.

Extreme ultraviolet (EUV) lithography technology empowers integrated circuit industry to mass produce chips with smaller pitches and higher density. Along with EUV tool advancement, significant progress has also been made in the development and advancement of EUV chemically amplified resist (CAR) materials, which allows for the improvement of resolution, line edge roughness, and sensitivity (RLS) trade-off. The scarce number of EUV photons has triggered the development of resist material with high absorption at 13.5 nm. However, a review of open literature reveals very limited reports on the effect of high EUV absorption elements on etch properties of advanced EUV resist. To ensure Moore’s Law continues to move forward, further resist performance improvement is required. In this regard, stochastic defects originating from photon shot noise, materials, and processing variabilities present a unique challenge for the extension of CAR platform for the patterning of smaller nodes. Notably, less attention has been paid to defects formed during the etching process used for pattern transfer. In this paper, we report on the relationship between resist make-up and etch properties. In particular, the effect of incorporation of EUV high absorbing elements are examined. New resist material design strategies for continuous improvement of EUV CAR lithographic performance will be discussed.

As device scale down to sub 3nm, NMOS/PMOS boundary patterning becomes critical in logic product. This patterning requires highly directional etching while maintaining high selectivity to the base metal layer. In this paper, we demonstrated that the ion energy has the trade-off between the profile verticality and the surface damage. The ion energy was strongly controlled by the bias voltage and surface damage was improved with lower bias voltage, but profile verticality was deteriorated because of the ion angle dispersion. To enhance the profile verticality the carbon rich gas was added as the top passivation. The proposed method will be a practical in sub-3nm logic boundary patterning.

Gate-all-around (GAA) nanosheet transistors are widely accepted for the mainstream technology towards 3nm technology node. The major strategy is to form nanosheet by using Si_1-xGe_x/Si multilayer structures (MLS). Inner spacer formation is a critical step as it defines the gate length and isolates gate from source and drain. Selectively removing of SiGe layers determines the dimension of the inner spacer and impacts the transistor performance significantly. It requires precise process control in the lateral cavity etching and brings significant challenges to conventional etching manners. In our previous work, we achieved isotropic Si_0.7Ge0.3 selective etching in SiGe/Si stack with high selectivity. However, the results were achieved on the single SiGe/Si stack in a relatively open area, when moving to dense patterns, the etching performance desires for further study. In this paper, we present our latest progress on isotropic etching by using ICP with mixed gas of CF₄/O₂/He on SiGe/Si stack periodic arrays. Loading effect and Si surface damage were observed. We reproduce these etching effects by developing an analytical model. This model is based on Monte-Carlo method and is capable of simulating the profile evolution of the lateral etching of SiGe/Si structures. The influence of etch time, pattern pitch and stack layer thickness on lateral etch results have been studied by simulation.

Gate-all-around nanosheet (GAA-NS) transistors are commonly considered to be most competitive logic device in the future. In the GAA nanosheet transistor device fabrication process, the inner spacer formation is a critical step as it physically isolates the gate from the source/drain, and defines the gate length. After the selective lateral etch of the SiGe in alternative Si/SiGe stack, inner spacer material is deposited and SiN_x is commonly used. This gap filling process demands for highly uniform growth of materials in order to minimize transistor variability. As moving to three-dimensional stacked structure, lateral open features bring challenges to conventional deposition manners such as chemical vapor deposition (CVD). In our previous work, we have compared the filling performance between low-pressure chemical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD), and demonstrated good SiN_x growth conformity by LPCVD in Si/SiGe indentation cavities. The cavity geometry was also found to pose significant impact on growth profile. However these works were carried out on isolated Si/SiGe nanosheet structure without neighboring unit. CVD process performance may degrade when moving from isolated to dense structures, especially when the critical dimension goes into tens of nanometers. In this paper, we present our latest simulation progress on the profile evolution of SiN_x CVD in dense Si/SiGe nanosheet structures with varying geometry and density of units. The SiN_x profile simulation indicates that LPCVD still maintains promising coverage performance in cavities, the SiN_x film thickness in the inner and outer side of unit are pretty close, while necking signature emerges near the unit top as process time increases. In contrast, PECVD exhibits pin holes within the cavity at the beginning of process, and the necking effect is relatively severe both in the cavity and near top of unit. We conduct systematic study on periodic stack structure array with different SiGe indentations. Pin holes are observed and get more pronounced in the PECVD process when the space between units is narrowed down. As the indentation decreases, pin holes become much smaller and exhibit better filling performance inside the lateral cavity.

Etching selectivity is the most critical factor in etch process, in which it can reduce non-etching materials loss while removing target materials. Silicon-germanium (SiGe) and silicon etch characteristic are similar, so the method to distinguish them during etching is a popular research topic. CF4-based mixed gases were applied for the SiGe to Silicon offline etch selectivity study. In terms of DoE (Design of Experiment) method, 5 process parameters, like CF4 gas, O2 gas, RF (resonant frequency) power and chamber pressure, were chosen to compose process conditions for SiGe and Si control wafer test. Based on uniform design, 15-run U15(55) design conditions were tested, and then subset selection algorithms was applied in R software to establish linear regression function for the process parameters. The correlation chart and heating map showed that dry plasma energy control was strongly with pressure and power simultaneous tuning direction and helium gas flow had little effect on SiGe-Si selectivity, which offered the tuning suggestion for SiGe-Si selectivity improvement.

The IC assembly industry has gone a full circle over the course of 50 years. At the beginning, everything was discretely packaged, but with the introduction of integrated circuits and advancement of lithograph y technologies, we were able to keep putting more into less., Yet the industry is facing challenges in continuing the scaling trend without sacrificing th e economic gain, therefore they turned to the heterogeneous integration, where the different IP blocks on the SOC were, once again, split into several discrete IC chips, thereby completing the circle. How do we enable these physically separated chips to have a performance that is on par with a single SOC? The answer is advanced packaging.