Proximity electron lithography (PEL) using the ultra-thin tri-layer resist system has been successfully integrated in our dual-damascene Cu/low-k interconnects technology for the 90-nm node. Critical comparison between conventional ArF lithography and PEL as to the via-chain yield for test element groups (TEGs) including approximately 2.9 million via chains was performed to demonstrate its production feasibility.
We report the first evaluation results for the printability and detectability of mask defects on a 1x stencil mask as used for proximity electron lithography (PEL). The defect printability has been defined for the patterns after the multi-step etching process through the tri-layer resist system inherently required for the use of low-energy electrons and the substrate. According to the three-dimensional lithography simulation, this definition is preferable to the conventional one based on the resist patterns prior to the etching process in the point that smoothing effects on defects are automatically taken into account. The critical size of printable defects as defined is 22 nm for 140 nm contact holes, while the stringent value of 16 nm is predicted in the conventional definition. Also, the detectability of the printable defects has been assessed by using the transmission electron-beam (EB) inspection tool. The assessment has been performed for both programmed defects and real defects occurred in contact-hole arrays. For the programmed defects, the perfect repeatability has been demonstrated for all the defects with printable sizes. In addition, real defects with the size of 15 nm have been successfully detected in the contact-hole arrays. Therefore, this study has demonstrated the manufacturability of PEL masks from the viewpoint of defect inspection.
A production-compatible method for the correction of image-placement (IP) error over a 1x stencil mask as used for proximity electron lithography (PEL) has been demonstrated. The mask IP error as measured using a newly developed metrology tool was fed forward to the PEL stepper, LEEPL-3000 and corrected for via the fine deflection of the electron beam. The overlay errors with respect to the substrate patterned by the ArF scanner have decreased from 63.6/59.3 nm to 26.1/36.4 nm in the x/y directions, but they are still larger than the errors of 15.2/14.8 nm for the conventional feedback method. Therefore, some improvements in the metrology method, the mask chucking method, the mask flatness and so on are required.
KEYWORDS: Data processing, Photomasks, Chemical elements, Error analysis, Finite element methods, Electron beam lithography, Distortion, Lithography, Computer simulations, Image processing
Image placement (IP) error of a 1x stencil mask is a concern for proximity electron beam lithography (PEL) when considering its application in the 65 and 45-nm nodes. According to our preliminary overlay budget for the 65-nm node, the global IP over the mask and the local IP within each membrane should be kept less than 10 and 7 nm, respectively to fulfill the total overlay accuracy of 23 nm. In this paper, we demonstrate the mask structure and the data processing method that enables the mask to be fully compatible with the local IP requirement in those technology nodes.
The lithographic performance of the low-energy electron-beam proximity-projection lithography (LEEPL) tool is demonstrated in terms of printability and overlay accuracy to establish the feasibility of proximity electron lithography (PEL) for the 65-nm technology node. The CD uniformity of 5.8 nm is achieved for the 1× stencil mask, and the mask patterns are transferred onto chemically amplified resist layers, coupled with a conformal multilayer process with the mask-error enhancement factor of nearly unity. Meanwhile, the overlay accuracy of 27.8 nm is achieved in the context of mix and match with the ArF scanner, and it is also shown that real-time correction for chip magnification, enabled by the use of die-by-die alignment and electron beam, can further reduce the error down to 21.3 nm. On the basis of the printability of programmed defects, it is shown that the most critical challenge to be solved for the application to production is the quality assurance of masks such as defect inspection and repair.
In order to clarify the direction of the lithography for the 45 nm node, the feasibilities of various lithographic techniques for gate, metal, and contact layers are studied by using experimental data and aerial image simulations. The focus and exposure budget have been determined from the actual data and the realistic estimation such as the focus distributions across a wafer measured by the phase shift focus monitor (PSFM), the focus and exposure reproducibility of the latest exposure tools, and the anticipated 45 nm device topography, etc. 193 nm lithography with a numerical aperture (NA) of 0.93 achieves the half pitch of 70 nm (hp70) by using an attenuated phase shift mask (att-PSM) and annular illumination. 193 nm immersion lithography has the possibility to achieve the hp60 without an alternative PSM (alt-PSM). For a gate layer, 50-nm/130-nm line-and-space (L/S) patterns as well as 50 nm isolated lines can be fabricated by an alt-PSM. Although specific aberrations degrade the critical dimension (CD) variation of an alt-PSM, ±2.6 nm CD uniformity (CDU) is demonstrated by choosing the well-controlled projection lens and using a high flatness wafer. For a contact layers, printing 90 nm contacts is very critical by optical lithography even if the aggressive resolution enhancement technique (RET) is used. Especially for dense contact, the mask error factor (MEF) increases to around 10 and practical process margin is not available at all. On the other hand, low-energy electron-beam proximity-projection lithography (LEEPL) can fabricate 80 nm contact with large process margin. As a lithography tool for the contact layers of the 45 nm node devices, LEEPL is expected to replace 193 nm lithography.
Low-energy electron-beam proximity-projection lithography (LEEPL) is considered the best candidate for the next-generation lithography (NGL) tool because a production tool will be available for 65nm-node mass production. Resolution capability has already exceeded the 65nm-node requirement and possibly also the 45nm-node requirement. Although LEEPL requires a resist less than 100nm thick to obtain the resolution, our tri-layer resist process provides the critical-dimension (CD) uniformity and dry-etching resistance necessary for fabricating 90nm-node via holes. As regards an overlay, a LEEPL tool aligned to an under layer printed by an ArF scanner attained 21.3nm (three sigma) overlay error, which exceeds the requirement for the 65nm node. Another concern with LEEPL application is mask contamination growth during exposure, however the contamination growth rate is gradual that the CD shift due to the contamination is under control. We applied LEEPL to 90nm-node via hole fabrication to examine whether it provides a higher resolution than an ArF scanner. We determined that the electrical-resistance limit for LEEPL is approximately 100nm diameter for a via hole and the limit for an ArF scanner is approximately 125nm diameter. Even without process optimization, LEEPL showed its advantages for via-hole fabrication over an ArF scanner.
The performance of the LEEPL production tool is discussed from the framework of the litho-and-mask concurrent development schemes to establish the feasibility of proximity electron lithography (PEL) especially for contact and via layers in the 65-nm technology node. The critical-dimension (CD) uniformity of 4.7 nm has been achieved for 90-nm contact holes over the 1x stencil mask. Thus, the mask patterns can be transferred onto the resist layer with CD errors of less than 10%, even if the mask-error enhancement factor (MEEF) of 1.6 is taken into account. The mask manufacturability is improved if the MEEF further decreases via the use of thinner resists. Meanwhile, the overlay accuracy of 21.1 nm has been achieved in mix-and-match with the ArF scanner, with the intra-field error of only 5.1 nm owing to the real-time correction for the mask distortion. Also, the conditions for splitting dense lines into two complementary portions have been determined to avoid the pattern collapse in wet-cleaning and drying processes. The critical length of 2 mm is fairly safe for 70-nm lines if the low-damage drying is employed. The inspection tool based on transmission electron images cannot detect all printable defects without further optimization, hence a future challenge.
The placement-error correction for low-energy electron-beam proximity-projection lithography (LEEPL) has been demonstrated to enable the overlay accuracy of 23 nm that meets the requirement for the 65-nm node. The overlay accuracy for LEEPL-ArF mix-and-match lithography has been analyzed, focusing separately on the intra-field error, the inter-field error, and the dynamic fluctuation over different wafers. It has been found that the intra-field error, mainly due to the distortion of a 1x stencil mask, can be effectively corrected for by using the fine deflection of the electron beam, a unique capability of the LEEPL exposure equipment. In addition, the inter-field error can be suppressed by correcting in real time for the magnification error of each chip detected by the die-by-die alignment system. The dynamic variation in the total overlay error is also small, and the overall alignment accuracy is fairly compatible with the preliminary overlay budget.
The practical methods for splitting line-and-space (LS) patterns and large rectangles into two complementary portions have been developed for the fabrication of stencil masks. The critical length for LS patterns can be determined from the finite-element modeling of the patterns under the external force acting up them in the wet cleaning of the mask. The optimal way of placing the split portions over the mask has also been demonstrated. On the other hand, a large pattern should be split in a step larger than half the shorter side of the figure. Since the methods are based on the simple and fast modeling, the flexible criteria as a function of design rule can be set in the splitting algorithm.
We propose the efficient on-site use of a 1x stencil mask for proximity electron lithography (PEL) for controlling image placement (IP) and critical dimension (CD). It has been demonstrated that the integrated approach to the IP-error correction on the mask-fabrication level using the data manipulation and the mask-exposure level using the deflection of an electron beam (EB) can meet the requirement for the overlay accuracy in the 65-nm technology node. Also, the time-dependent variation in mask CD due to EB-assisted contamination growth can be managed by using the combination of the dose control and the periodic dry cleaning of the mask.
The critical-dimension (CD) performance and the printability of 1x stencil masks used for low-energy electron-beam proximity-projection lithography (LEEPL) have been studied by using the LEEPL β-tool. The CD uniformity and the line edge roughness on the mask are 6.0 nm and 3.5 nm in 3σ, respectively. It has been found that the fidelity of the etching process is so high that the optimization of the electron-beam writing process is critical to perforate high-quality patterns. The mask error enhancement factor evaluated over 80-100 nm lies is nearly unity, demonstrating the excellent fidelity of image transfer from the mask to a wafer. The critical defect sizes are 14.5 and 22.8 nm for the protrusions on the edges of 100-nm lines and the 150-nm contact holes respectively, implying that defect inspection is a challenge. The current achievements and the final targets in the 65-nm node are compared to assess the gap that must be bridged.
In order to solve the various problems associated with a LEEPL mask as originally demonstrated in the form of single-membrane diamond mask, we propose a new mask format termed COSMOS (complementary stencil mask on strut-supports). The COSMOS has small-area membranes with strut reinforcement and is somewhat similar to the masks used for other types of electron projection lithography (EPL). However, the exposure strategy is completely different from the other EPLs; a complete pattern image can be transcribed by overlaying complementary portions of a mask pattern via multiple exposures. The inter-membrane and intra-membrane distortions of image placement have been computed by the finite element method (FEM) simulation. It is concluded that the global distortion induced by the inversion of gravity can be corrected for by mask writing, and the intra-membrane distortion, induced by both the gravitational flexure of a membrane and the pattern density distribution, can be neglected with the membrane intrinsic stress of approximately 5 Mpa..
KEYWORDS: Photomasks, Charged-particle lithography, Chemical elements, Data processing, Lithography, Distortion, Finite element methods, Image processing, Optical lithography, Data conversion
We have been developing a practical mask-data processing system for low-energy electron-beam proximity-projection lithography (LEEPL), a promising candidate for the next generation lithography. Several problems inherent to the unique mask structure for LEEPL have been solved in principle. In this paper, the overview of the system is demonstrated, with special focus on the corrections for the possible violation of complementary splitting on the boundary of neighboring data-processing units as well as the image placement error due to mask distortion.
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