In world-leading semiconductor manufacturing, the device feature size keeps on reducing and with it processes become more challenging in the next technology node. The On Product Overlay (OPO) budget is therefore required to reduce further. Alignment is one of the key factors in reducing overlay wafer to wafer (W2W) variations. To save product area and reduce scribe line width, small alignment mark is evaluated to achieve the similar results as reference mark and to optimize the OPO performance. In this work, we will show the experimental results of small alignment mark and investigate the on product overlay performance by simulation.
In world-leading semiconductor manufacturing, the device feature size keeps on reducing and with it processes become more challenging in the next technology node. The on-product overlay budget is therefore required to reduce further. Alignment is one of the key factors in reducing overlay wafer-to-wafer variation. Due to the complexity, a holistic methodology is used to combine various alignment solutions to achieve the optimal on-product overlay performance. In this paper, we evaluated the holistic method by simulation and experiment for DUV layers. We illustrate the expected on-product overlay improvement.
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