Mr. Chia Wei Huang Profile

Chia Wei Huang

at United Microelectronics Corp

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Author

Publications (5)

Proceedings Article | 26 May 2022 Poster + Paper

Using pattern analysis to improve wafer inspection flow

Hung-yu Lin, Ethan Wang, Jason Sweis, Philippe Hurat, Ya-Chieh Lai, Yu-Chin Pai, Ku Fang, Chin-Juan Li, Chia Wei Huang, Jun-Ming Chen, Yung-Feng Cheng

Proceedings Volume 12053, 120531T (2022) https://doi.org/10.1117/12.2613620

KEYWORDS: Inspection, Semiconducting wafers, Wafer inspection, Image classification, Yield improvement, Defect inspection, Data analysis, Software development, Defect detection, Tolerancing

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Proceedings Article | 13 March 2009 Paper

Implementing a framework to generate a unified OPC database from different EDA vendors for 45nm and beyond

Shady Abdelwahed, Mohamed Al-Iman, Rami Fathy, Nader Hindawy, Jochen Schacht, Regina Shen, Chia Wei Huang, Pei Ru Tsai, Te Hung Wu, Chuen Huei Yang

Proceedings Volume 7275, 72751O (2009) https://doi.org/10.1117/12.816281

KEYWORDS: Optical proximity correction, Electronic design automation, Photomasks, Semiconducting wafers, Data modeling, SRAF, Visualization, Wafer-level optics, Databases, Lithography

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Proceedings Article | 26 March 2007 Paper

SEM based data extraction for model calibration

Mohamed Al-Imam, H. Y. Liao, Jochen Schacht, George Bailey, Te Hung Wu, Chia Wei Huang, Sheng Yuan Huang, Pei Ru Tsai, Chuen Huei Yang

Proceedings Volume 6520, 65203B (2007) https://doi.org/10.1117/12.707353

KEYWORDS: Data modeling, Scanning electron microscopy, Calibration, Process modeling, Image processing, Optical proximity correction, Semiconducting wafers, Metrology, Resolution enhancement technologies, Feature extraction

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The model calibration process, in a resolution enhancement technique (RET) flow, is one of the most critical steps towards building an accurate OPC recipe. RET simulation platforms use models for predicting latent images in the wafer due to exposure of different design layouts. Accurate models can precisely capture the proximity effects for the lithographic process and help RET engineers build the proper recipes to obtain high yield. To calibrate OPC models, test geometries are created and exposed through the lithography environment that we want to model, and metrology data are collected for these geometries. This data is then used to tune or calibrate the model parameters. Metrology tools usually provide critical dimension (CD) data and not edge placement error (EPE - the displacement between the polygon and resist edge) data however model calibration requires EPE data for simulation. To work around this problem, only symmetrical geometries are used since, having this constraint, EPE can be easily extracted from CD measurements. In real designs, it is more likely to encounter asymmetrical structures as well as complex 2D structures that cannot easily be made symmetrical, especially when we talk about technology nodes for 65nm and beyond. The absence of 2D and asymmetric test structures in the calibration process would require models to interpolate or extrapolate the EPE's for these structures in a real design. In this paper we present an approach to extract the EPE information from both SEM images and contours extracted by the metrology tools for structures on test wafers, and directly use them in the calibration of a 55nm poly process. These new EPE structures would now mimic the complexity of real 2D designs. Each of these structures can be individually weighed according to the data variance. Model accuracy is then compared to the conventional method of calibration using symmetrical data only. The paper also illustrates the ability of the new flow to extract more accurate measurement out of wafer data that are more immune to errors compared to the conventional method.

Proceedings Article | 26 March 2007 Paper

The calibration of process window model for 55-nm node

Te Hung Wu, Sheng Yuan Huang, Chia Wei Huang, Pei Ru Tsai, Chuen Huei Yang, Irene Yi-Ju Su, Brad Falch

Proceedings Volume 6520, 65203A (2007) https://doi.org/10.1117/12.715496

KEYWORDS: Semiconducting wafers, Data modeling, Process modeling, Calibration, Optical proximity correction, Finite element methods, Sensors, Lithography, Tolerancing

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Proceedings Article | 21 March 2007 Paper

A systematic approach for capturing interconnects hot spots

Mohamed Al-Imam, H. Y. Liao, Jochen Schacht, Te Hung Wu, Chia Wei Huang, Shen Yuan Huang, Pei Ru Tsai, Chuen Huei Yang

Proceedings Volume 6521, 65211C (2007) https://doi.org/10.1117/12.713521

KEYWORDS: Semiconducting wafers, Photomasks, Image processing, Overlay metrology, Integrated circuits, Lithography, Resistance, Classification systems, Integrated circuit design, Transistors

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