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Using a pattern-based approach to detect all IP Blocks used provides the foundry advanced capabilities to analyze them further for any kind of changes which could void the OPC and process window optimizations. Having any changes in an IP Block could cause functionality changes or even failures. This also opens the foundry to legal and cost issues while at the same time forcing re-spins of the design.
In this publication, we discuss the methodology we have employed to avoid process issues and tape-out errors while at the same time reduce our manual work and improve the turnaround time. We are also able to use our pattern analysis to improve our OPC optimizations when modifications are encountered which have not been seen before.
This paper will present a working flow for using design diffing techniques to extract layout structures and perform a geometry analysis flow combined with testing results to find most probable suspects that may cause noticeable yield loss.
This paper will present a working flow for using pattern analysis interlayer profiling techniques to turn multiple layer physical info into group linked parameter values. Using this data analysis flow combined with an electrical model allows us to find critical regions on a layout for yield learning.
This paper will present a novel method of how to generate a complete profile of components for any particular design. The component checking flow need to be completed within hours so it will have very little impact on the tape-out time. A pre-layer checking method is also run to group commonly used layers for different electrical components and then employ different layout profiling flows. The foundry does this design chip analysis in order to find potentially weak devices due to their size or special size requirements for particular electrical components. The foundry can then take pre-emptive action to avoid yield loss or make an unnecessary mask for new incoming products before fab processing starts.
This paper will present a working flow for using design analysis techniques combined with diagnostic methods to systematically transform silicon testing information into physical layout information. A new set of the testing results are received from a new lot of wafers for the same product. We can then correlate all the diagnostic results from different periods of time to check which blocks or nets have been highlighted or stop occurring on the failure reports in order to monitor process changes which impact the yield. The design characteristic analysis flow is also implemented to find 1) the block connections on a design that have failed electrical test or 2) frequently used cells that been highlighted multiple times.
This paper will present a smart and efficient working flow that can map inspection data back onto a design and produce more diverse monitor points for inspection, and each set of monitor points links to a set of statistical design data that shows insight on design structures that are more sensitive to the process variations. A full-chip post-processing flow is also implemented to process design layout so that the particular patterns that may cause certain function blocks to fail can be directly checked on post-processed layout.
This paper will present a novel methodology to enumerate initial test patterns based on other technology node products. With this novel methodology, DRM development and process capability verification can be sped up rapidly in comparison to a more traditional way. At the same time, the process weak-point signatures can be migrated from the older technology nodes to the new technology node for verification. This methodology will help foundries catch process detractor patterns at new technology early development stage.
For debugging silicon failures, DFT diagnostics can identify which nets or cells caused the yield loss. But normally, a long time period is needed with many resources to identify which failures are due to one common layout pattern or structure. This paper will present a new yield diagnostic flow, based on preliminary EFA results, to show how pattern analysis can more efficiently detect pattern related systematic defects. Increased visibility on design pattern related failures also allows more precise yield loss estimation.
This paper presents a novel method of how to generate test key patterns which contain known problematic patterns as well as any constructs which designers could possibly draw based on current design rules. The enumerated test key patterns will contain the most critical design structures which are allowed by any particular design rule. A layout profiling method is used to do design chip analysis in order to find potential weak points on new incoming products so fab can take preemptive action to avoid yield loss. It can be achieved by comparing different products and leveraging the knowledge learned from previous manufactured chips to find possible yield detractors.
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