The application of overlay run-to-run control in high-mix production fabs (such as development fabs, ASIC fabs or foundries) encounters some unique problems. A new observer algorithm called JADETM (Just-in-Time Adaptive Disturbance Estimation) was developed to solve the high-mix run-to-run control problem. JADE uses recursive weighted least-squares parameter estimation to identify the contributions to variation that are dependent upon tool, product, reference tool, and reference reticle. With the JADE Observer algorithm, run-to-run controllers use all available feedback data independent of the length of time since a particular product was processed. The application of JADE, compared to traditional control techniques, will be demonstrated on high and low-mix fab lithography overlay data. This comparison illustrates the degradation of the typical streamline observer formulation under high-mix operation, with an actual worsening of overlay control relative to open-loop (no run-to-run control) operation. In contrast, the JADE algorithm control performance, while matching the typical streamline formulation at low-mix operation, will be shown to be unaffected under very high-mix photolithography operation.
KEYWORDS: Semiconducting wafers, Thermal modeling, Low pressure chemical vapor deposition, Chemical elements, Temperature metrology, Data modeling, Quartz, Numerical integration, Chemical vapor deposition, Monte Carlo methods
This paper presents a new first principles thermal model to predict wafer temperatures within a hot-wall Low Pressure Chemical Vapor Deposition (LPCVD) furnace based on furnace wall temperatures as measured by thermocouples. This model is based on an energy balance of the furnace system with the following features:
(a) the model is a transformed linear model which captures the nonlinear relationship between the furnace wall temperature distribution and the wafer temperature distribution, (b) the model can be solved with a direct algorithm instead of iterative algorithms used in all existing thermal models, eliminating potential problems with convergence and local minima related to optimization, and (c) finite area to finite area methods are applied to calculate configuration factors, avoiding the implementation difficulties of numerical integration. The simplicity of the model form makes the model useful for model based run-to-run control. The model predictions agree with experimental data very well. The sensitivity of wafer temperatures to furnace wall temperatures is given
analytically. More uniform wafer temperature profile is obtained via optimization.
KEYWORDS: Process modeling, Adaptive control, Process control, Control systems, Manufacturing, Chemical mechanical planarization, System identification, Computing systems, Device simulation, Microelectronics
It is a common practice in today's microelectronics manufacturing facilities to have many different products and processes run on each processing tool. This is caused mainly by the high capital costs associated with the tools and the limited capacity of the facility. A run-to-run controller relies on having a model that is consistent from run to run. When the different processes run on the tool are significantly different, the controller may behave unexpectedly because each change to a new process can appear as a large disturbance. In addition, it may take several successive runs of a given process for the controller to stabilize, but this cannot happen if the processes change too often. Ideally, the controller should be able to determine optimal settings for all processes that must run on the tool, regardless of the order in which they appear. In an adaptive control strategy, an online system identification scheme runs along with the controller and constantly adjusts the model so that it mimics the true behavior of the system. One very difficult task in this situation is determining whether observed errors in the output are due to errors in accounting for tool differences or for product differences. This discussion will outline a scheme for deciding which model parameters are in error and performing the correct model updates.
Lithography overlay refers to the measurement of the alignment of successive patterns within the manufacture of semiconductor devices. Control of overlay has become of great importance in semiconductor manufacturing, as the tolerance for overlay error is continually shrinking in order to manufacture next-generation semiconductor products. Run-to-run control has become an attractive solution to many control problems within the industry, including overlay. The term run-to-run control refers to any automated procedure whereby recipe settings are updated between successive process runs in order to keep the process under control. The following discussion will present the formulation of such a controller by examining control of overlay. A brief introduction of overlay will be given, highlighting the control challenge overlay presents. A data management methodology that groups like processes together in order to improve controllability, referred to as control threads, will then be presented. Finally, a discussion of linear model predictive control will show its utility in feedback run-to-run control.
Formation of the MOS-FET polysilicon gate structure is a critical step in integrated circuit manufacturing. Control of poly-gate Critical Dimension (CD's) greatly affects revenue from microprocessor production. Poly-gate CD's correlate strongly to speed. As a result, variation in CD control causes unsaleable slow parts, high revenue fast parts, or scrapped high leakage product from overly fast parts. Controlling to the optimal value CD value, however, it is a difficult task due to the continual drift and step changes that occur in the photolithography and etch tools. As a result of this need, AMD's Fab 25 developed an automated run-to-run controller of poly-gate CD's as part of an Advanced Process Control (APC) initiative. From the perspective of both control and manufacturability, Fab 25's Run-to-Run controller of poly-gate Critical Dimension (CD) has been a critical enabler of our success in manufacturing the K6 product. This paper discusses the architecture, algorithm and results of the poly-gate CD control system.
A chemical kinetic rate model for the deposition of titanium nitride films from the surface reaction of tetrakis(dimethyl-amido)titanium (TDMAT) was developed. Without ammonia addition, TDMAT forms a titanium nitride film by pyrolyzing on the hot substrate surface. Experimental data from the applied materials 5000 deposition tool was modeled using a CSTR formulation. With the parameters of the surface reaction model regressed to fit portions of the experimental results, reasonably accurate model predictions over the entire domain of experimental data were obtained.
KEYWORDS: Polishing, Semiconducting wafers, Chemical mechanical planarization, Process control, Data modeling, Surface finishing, Process modeling, Silicon, Dielectrics, Manufacturing
Chemical mechanical polishing (CMP) of silicon oxide interlayer dielectric is a critical process in modern multi- layer metal integrated circuit manufacturing. In this process, the rate of planarization of features on a silicon wafer surface changes with age of the polishing pad. This effect creates the need for adjustment of polishing times to compensate for changes in planarization rates. The way that planarization rate varies with polish time must be defined to develop robust control of this process. In this work, a theoretical model for the dependence of planarization rate on polish time was developed. This model was then applied to data from a Westech 472 CMP system and shown to accurately capture the time variation of measured removal rates. A control algorithm using this model was tried using a different CMP tool, the Westech 372, creating a mismatch between the control model and process. Nonetheless, the control model quickly adapted to the new conditions and controlled the process well.
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