With the increasing complexity of semiconductor manufacturing processes, from early R&D through ramp and high-volume manufacturing (HVM), a myriad of data analysis solutions are required for fast and actionable decisions in a fab. In our previous work, we used the SEM metrology capabilities of aiSIGHT to perform shape analysis and defect detection of contact holes and pillars in tight-pitch DRAM structures such as storage node landing pad arrays (SNLP) to gain insights on process variability. This paper focuses on a different type of metrology application, extracting unbiased roughness from mask and wafer SEM images, such as unbiased line edge roughness (LER) and line width roughness (LWR), along with defect detection.
To maintain lithographic pitch scaling, extreme ultraviolet (EUV) processes have been adopted in high-volume manufacturing (HVM) for today’s advanced logic and memory devices. Among various defect sources, stochastic patterning defects are one of the most important yield detractors for EUV processes. In this work, we will limit our scope to patterning defects arising out of lithography. In the past, it has been shown that the patterning defect process window is often limited by stochastic hotspots. These hotspots have very low failure probabilities in a well-optimized process, and hence their detection necessitates large area sensitive defect inspection, such as with a broadband plasma (BBP) optical defect inspection system. It has also been shown that systematic issues in design can be exacerbated by stochastic variations. Hence, it is critical to discover these hotspots and study their variability with massive SEM metrology. Such analyses can uncover systematic trends, which can then be corrected and monitored. In this work, we discover hotspots using broadband plasma (BBP) optical inspection and study their variability using KLA’s aiSIGHT™ pattern-centric defect and metrology software solution for automatic defect classification and SEM metrology measurements. We also demonstrate the need for fast and rigorous 3D probabilistic stochastic defect detection on design as a continuation of this work.
The new generation of 10nm node DRAM devices have now adopted EUV based patterning techniques. With further shrink in design rules, single exposure EUV processes will be pushed further using advanced photoresists and new mask types. However, in absence of high NA EUV lithography ready for high volume manufacturing (HVM) until at least 2025, acceptable local CD (critical dimensions) uniformity and yielding process windows at low exposure dose are a challenge for single exposure EUV. Further, for EUV implementation in sub-32nm pitch DRAM capacitator patterning applications, multi-patterning techniques must be explored. In this paper, EUV based double-patterning techniques have been demonstrated to pattern honeycomb array contact holes and pillars. The processing utilizes two EUV masks, using simple angled line space patterns. We have explored two different types of double patterning options: litho-freeze-litho-etch (LFLE) to pattern contact holes and litho-etch-lithoetch (LELE) to pattern pillars. In the absence of high NA EUV, these processing techniques are useful to pattern tight pitch (e.g., 32nm) contact holes/pillars for newer generations of DRAM devices. Another key objective of this paper is to present a set of metrology characterization methods to enable proper process optimizations.
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