KEYWORDS: Computer programming, Electron beam direct write lithography, Raster graphics, Electron beam lithography, Image compression, Logic, Detection and tracking algorithms, Semiconducting wafers, Data compression, Data processing
Data throughput is a critical metric in a multiple electron-beam direct-write (MEBDW) system so that heavy-duty data processing equipment is required. The main challenge is about how to achieve high performance with cost-effective techniques. We propose a high compression rate algorithm for efficient data transfer and high speed decompression hardware to raise data throughput of the system. The hardware decoder uses pipeline architecture, a run-length encoding first-in-first-out queue, and parallel dispatch logic to increase the throughput. The decoder is evaluated on field-programmable gate array and simulated with layout images that are compressed using the proposed compression software. The results demonstrate 18.2% better compression rate and 254.8% better throughput than the previous work with similar hardware cost. Because no static random-access memory is used in the design, the channel numbers of the system can be easily scaled up, which makes it possible for the next-generation MEBDW system to achieve higher wafer per hour targets.
KEYWORDS: Electron beam lithography, Data compression, Computer programming, Clocks, Lutetium, Stereolithography, Electroluminescence, Data centers, Data processing, Field programmable gate arrays
A lossless electron-beam layout (EBL) data compression algorithm, LineDiff Entropy v2.0, and its low-complexity, high-performance hardware decoder for multiple electron-beam direct-write lithography systems are proposed. The algorithm compares consecutive data scanlines and encodes the data based on the change/no-change of pixel values and the lengths of pixel sequences. Then, the compaction steps of data omission, merging, and encoding of consecutive long identical scanlines are applied. Unique short codes are assigned to data with high occurrence frequency. The hardware decoder is designed as three circuit blocks that perform entropy decoding, decompaction, and EBL data generation through parallel outputs. The results demonstrate that our algorithm can achieve excellent compression performance and that the hardware decoder can decompress data at very high data rates.
KEYWORDS: Semiconducting wafers, Maskless lithography, Lithography, Photomasks, Data processing, Manufacturing, Electron beams, Data centers, Lenses, Microelectromechanical systems
Electron-beam lithography is promising for future manufacturing technology because it does not suffer from wavelength
limits set by light sources. Since single electron-beam lithography systems have a common problem in throughput, a
multi-electron-beam lithography (MEBL) system should be a feasible alternative using the concept of massive
parallelism. In this paper, we evaluate the advantages and the disadvantages of different MEBL system architectures,
and propose our novel Massively Parallel MaskLess Lithography System, MPML2.
MPML2 system is targeting for cost-effective manufacturing at the 32nm node and beyond. The key structure of the
proposed system is its beamlet array cells (BACs). Hundreds of BACs are uniformly arranged over the whole wafer area
in the proposed system. Each BAC has a data processor and an array of beamlets, and each beamlet consists of an
electron-beam source, a source controller, a set of electron lenses, a blanker, a deflector, and an electron detector. These
essential parts of beamlets are integrated using MEMS technology, which increases the density of beamlets and reduces
the system cost. The data processor in the BAC processes layout information coming off-chamber and dispatches them
to the corresponding beamlet to control its ON/OFF status. High manufacturing cost of masks is saved in maskless
lithography systems, however, immense mask data are needed to be handled and transmitted. Therefore, data
compression technique is applied to reduce required transmission bandwidth. The compression algorithm is fast and
efficient so that the real-time decoder can be implemented on-chip. Consequently, the proposed MPML2 can achieve 10
wafers per hour (WPH) throughput for 300mm-wafer systems.
This research shows the realization of 2.4-GHz film bulk acoustic wave (FBAW) filters. The design, simulation, fabrication, measurement, and analysis of the film bulk acoustic wave resonator (FBAR) devices are covered, which is helpful for the manufacture of the FBAR devices. The simulation of the FBAR and RF circuitry can be integrated on a single platform. The fabrication of the FBAW filters is compatible with complementary metal-oxide semiconductors. This device can be used in 2.4-GHz bandpass filters, such as 802.11b/g and Bluetooth. In this research, the 2.4-GHz FBAW filters for wireless communication have been accomplished. The fabricated FBAW filters have insertion loss of −10 dB, return loss of −7 dB, and stopband rejection of −25 dB, central frequency of 2.485 GHz, bandwidth of 60 MHz, and size of 0.5 mm×0.5 mm.
Due to non-ideal optical effects such as aberration and optical diffraction, printed poly gates on the wafer suffer from
across-gate linewidth variation (AGLV) and across-chip linewidth variation (ACLV,) especially in the subwavelength
regime. The poly gate distortion affects device electrical characteristics, including drive current (Ion), leakage current
(Ioff), and threshold voltage (Vt). For circuits sensitive to layout, such as compact memory cells, electrical performances
can vary with image distortion of each transistor even after applying resolution enhancement technologies (RETs) such
as optical proximity corrections. In this paper, we demonstrate the impact of OPC settings on the performance of 6T-SRAM
cells. The printed transistor gate and active region patterns are simulated by an in-house OPC engine. The device
model for each distorted transistor is then extracted based on approximating each distorted channel pattern with a set of
smaller rectangles. Consequently, Electrical performance such as static noise margin (SNM) can be obtained by
incorporating these extracted device models into a circuit simulator. Preliminary results show that OPC settings such as
segmentation length and numbers of corrections can affect wafer image quality and electrical performance in different
ways.
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