Dr. Abdelkarim Mercha Profile

Dr. Abdelkarim Mercha

at IMEC

SPIE Involvement:

Author

Publications (12)

Proceedings Article | 16 March 2016 Paper

Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs

Trong Huynh-Bao, Julien Ryckaert, Sushil Sakhare, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Piet Wambacq

Proceedings Volume 9781, 978102 (2016) https://doi.org/10.1117/12.2218361

KEYWORDS: Nanowires, Field effect transistors, Extreme ultraviolet lithography, Design for manufacturability, Manufacturing, Transistors, Metals, Lithography, Logic, Optical lithography, Photovoltaics, Gallium arsenide, CMOS technology, Diffusion, Electrodes

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SPIE Journal Paper | 25 February 2016

Architectural strategies in standard-cell design for the 7 nm and beyond technology node

Syed Muhammad Yasser Sherazi, Bharani Chava, Peter Debacker, Marie Garcia Bardon, Pieter Schuddinck, Farshad Firouzi, Praveen Raghavan, Abdelkarim Mercha, Diederik Verkest, Julien Ryckaert

JM3, Vol. 15, Issue 01, 013507, (February 2016) https://doi.org/10.1117/12.10.1117/1.JMM.15.1.013507

KEYWORDS: Optical lithography, Metals, Copper, Resistance, Extreme ultraviolet, Tungsten, Back end of line, Critical dimension metrology, Capacitance, CMOS technology

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Proceedings Article | 16 April 2015 Paper

Maintaining Moore’s law: enabling cost-friendly dimensional scaling

Arindam Mallik, Julien Ryckaert, Abdelkarim Mercha, Diederik Verkest, Kurt Ronse, Aaron Thean

Proceedings Volume 9422, 94221N (2015) https://doi.org/10.1117/12.2086085

KEYWORDS: Extreme ultraviolet lithography, Optical lithography, Surface plasmons, Extreme ultraviolet, Photomasks, Back end of line, Lithography, Metals, Semiconducting wafers, Semiconductors

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Proceedings Article | 18 March 2015 Paper

Impact of a SADP flow on the design and process for N10/N7 metal layers

W. Gillijns, S. M. Y. Sherazi, D. Trivkovic, B. Chava, B. Vandewalle, V. Gerousis, P. Raghavan, J. Ryckaert, K. Mercha, D. Verkest, G. McIntyre, K. Ronse

Proceedings Volume 9427, 942709 (2015) https://doi.org/10.1117/12.2085923

KEYWORDS: Metals, Photomasks, Semiconducting wafers, Lithography, Optical lithography, Standards development, Capacitance, Optical proximity correction, Scanning electron microscopy, Manufacturing

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Proceedings Article | 18 March 2015 Paper

Standard cell design in N7: EUV vs. immersion

Bharani Chava, David Rio, Yasser Sherazi, Darko Trivkovic, Werner Gillijns, Peter Debacker, Praveen Raghavan, Ahmad Elsaid, Mircea Dusa, Abdelkarim Mercha, Julien Ryckaert, Diederik Verkest

Proceedings Volume 9427, 94270E (2015) https://doi.org/10.1117/12.2085739

KEYWORDS: Extreme ultraviolet, Photovoltaics, Deep ultraviolet, Standards development, Extreme ultraviolet lithography, Lithography, Photomasks, Source mask optimization, Scanners, Optical lithography

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Proceedings Article | 18 March 2015 Paper

DTCO at N7 and beyond: patterning and electrical compromises and opportunities

Julien Ryckaert, Praveen Raghavan, Pieter Schuddinck, Huynh Bao Trong, Arindam Mallik, Sushil Sakhare, Bharani Chava, Yasser Sherazi, Philippe Leray, Abdelkarim Mercha, Jürgen Bömmels, Gregory McIntyre, Kurt Ronse, Aaron Thean, Zsolt Tökei, An Steegen, Diederik Verkest

Proceedings Volume 9427, 94270C (2015) https://doi.org/10.1117/12.2178997

KEYWORDS: Optical lithography, Metals, Transistors, Standards development, Logic, Resistance, Lithography, Extreme ultraviolet, Extreme ultraviolet lithography, Field effect transistors

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Proceedings Article | 18 March 2015 Paper

Layout optimization and trade-off between 193i and EUV-based patterning for SRAM cells to improve performance and process variability at 7nm technology node

Sushil Sakhare, Darko Trivkovic, Tom Mountsier, Min-Soo Kim, Dan Mocuta, Julien Ryckaert, Abdelkarim Mercha, Diederik Verkest, Aaron Thean, Mircea Dusa

Proceedings Volume 9427, 94270O (2015) https://doi.org/10.1117/12.2086100

KEYWORDS: Optical lithography, Nano opto mechanical systems, Metals, Extreme ultraviolet lithography, Photomasks, Extreme ultraviolet, Critical dimension metrology, Scanners, Lithography, Reliability

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Proceedings Article | 17 April 2014 Paper

The economic impact of EUV lithography on critical process modules

Arindam Mallik, Naoto Horiguchi, Jürgen Bömmels, Aaron Thean, Kathy Barla, Geert Vandenberghe, Kurt Ronse, Julien Ryckaert, Abdelkarim Mercha, Laith Altimime, Diederik Verkest, An Steegen

Proceedings Volume 9048, 90481R (2014) https://doi.org/10.1117/12.2046310

KEYWORDS: Extreme ultraviolet lithography, Optical lithography, Lithography, Extreme ultraviolet, Semiconducting wafers, Semiconductors, Photomasks, Back end of line, Metals, Front end of line

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Proceedings Article | 8 April 2013 Paper

The need for EUV lithography at advanced technology for sustainable wafer cost

Arindam Mallik, Wim Vansumere, Julien Ryckaert, Abdelkarim Mercha, Naoto Horiguchi, Steven Demuynck, Jürgen Bömmels, Tokei Zsolt, Geert Vandenberghe, Kurt Ronse, Aaron Thean, Diederik Verkest, Hans Lebon, An Steegen

Proceedings Volume 8679, 86792Y (2013) https://doi.org/10.1117/12.2011528

KEYWORDS: Semiconducting wafers, Lithography, Extreme ultraviolet lithography, Extreme ultraviolet, Photomasks, Optical lithography, Semiconductors, Databases, Back end of line, 193nm lithography

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Proceedings Article | 24 March 2006 Paper

Impact of line width roughness on device performance

G. Lorusso, L. H. A. Leunissen, C. Gustin, A. Mercha, M. Jurczak, H. Marchman, A. Azordegan

Proceedings Volume 6152, 61520W (2006) https://doi.org/10.1117/12.656128

KEYWORDS: Line width roughness, Semiconducting wafers, Transistors, Critical dimension metrology, Electron beam lithography, Field effect transistors, Silicon, Line edge roughness, Photomasks, Metrology

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Proceedings Article | 25 May 2004 Paper

Impact of the back-gate bias on the low-frequency noise of partially depleted silicon-on-insulator MOSFETs

Nataliya Lukyanchikova, N. Garbar, A. Smolanka, Eddy Simoen, A. Mercha, Cor Claeys

Proceedings Volume 5470, (2004) https://doi.org/10.1117/12.546971

KEYWORDS: Field effect transistors, Silicon, Resistance, Oxides, Semiconducting wafers, Transistors, Time metrology, Measurement devices, Semiconductor physics, Ionization

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Proceedings Article | 25 May 2004 Paper

1/f noise in deep submicron CMOS technology for RF and analogue applications

Mercha Abdelkarim, Eddy Simoen, Stefaan Decoutere, Cor Claeys

Proceedings Volume 5470, (2004) https://doi.org/10.1117/12.546962

KEYWORDS: CMOS technology, Oxides, Field effect transistors, Dielectrics, Transistors, Analog electronics, Switching, System on a chip, Denoising, Oscillators

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Showing 5 of 12 publications

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