Sub-half-micron device fabricated with 2-um generation facilities

Kiyoshi Mori

doi:10.1117/12.323959

4 September 1998 Sub-half-micron device fabricated with 2-μm generation facilities

Kiyoshi Mori

Proceedings Volume 3506, Microelectronic Device Technology II; (1998) https://doi.org/10.1117/12.323959
Event: Microelectronic Manufacturing, 1998, Santa Clara, CA, United States

Abstract

A MOS transistor with a channel length under 0.20 micrometer was developed with the process equipment typically utilized for a conventional 2 micrometer device. The transistor was built on the vertical side walls of a 3 dimensional trench, thus achieving much higher channel width W, and lower channel length L than possible using 2 micrometer planar technology. The capability of having larger W coupled with non- photolithography limited L, gives this vertical MOS transistor great advantages in drain current I_DS, transconductance g_m, and operation frequency f_o over same technology planar transistors.

Citation Download Citation

Kiyoshi Mori "Sub-half-micron device fabricated with 2-μm generation facilities", Proc. SPIE 3506, Microelectronic Device Technology II, (4 September 1998); https://doi.org/10.1117/12.323959

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