Systematic methodology for optimizing the tradeoff of polysilicon depletion versus boron penetration in sub-0.18-um surface-channel PMOS devices

Gregory S. Scott; Samar K. Saha; Christopher S. Olsen; Faran Nouri; Jeffrey Lutze; Mark E. Rubin; Martin Manley

doi:10.1117/12.360543

1 September 1999 Systematic methodology for optimizing the tradeoff of polysilicon depletion versus boron penetration in sub-0.18-μm surface-channel PMOS devices

Gregory S. Scott, Samar K. Saha, Christopher S. Olsen, Faran Nouri, Jeffrey Lutze, Mark E. Rubin, Martin Manley

Author Affiliations +

Proceedings Volume 3881, Microelectronic Device Technology III; (1999) https://doi.org/10.1117/12.360543
Event: Microelectronic Manufacturing '99, 1999, Santa Clara, CA, United States

Abstract

Control of boron penetration in surface-channel PMOS devices is critical in order to ensure tight threshold voltage (V_t) distribution. Previous work has focused on studying relatively gross boron-penetration effects, which give rise to large shifts in V_t. In practice, low-voltage CMOS technologies are sensitive to small degradation in PMOS V_t scatter due to the onset of boron penetration. Moreover, the use of rapid thermal annealing can give rise to difficult trade-offs between poly depletion and boron penetration. As both of these effects can influence the PMOS V_t we propose a sensitive, systematic, methodology to distinguish between depletion and penetration effects and illustrate its application in a number of advanced CMOS processes, with oxide thickness ranging from 30-50 angstrom.

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Gregory S. Scott, Samar K. Saha, Christopher S. Olsen, Faran Nouri, Jeffrey Lutze, Mark E. Rubin, and Martin Manley "Systematic methodology for optimizing the tradeoff of polysilicon depletion versus boron penetration in sub-0.18-μm surface-channel PMOS devices", Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); https://doi.org/10.1117/12.360543

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