Sub-0.1-um vertical MOS transistor

Kiyoshi Mori

doi:10.1117/12.360569

1 September 1999 Sub-0.1-μm vertical MOS transistor

Kiyoshi Mori

Proceedings Volume 3881, Microelectronic Device Technology III; (1999) https://doi.org/10.1117/12.360569
Event: Microelectronic Manufacturing '99, 1999, Santa Clara, CA, United States

Abstract

A sub 0.1 microns channel length vertical MOS transistor was developed for processing with equipment typically utilized for older generation devices. One of the important advantages of vertical MOS transistor technology is that the channel length scaling is not limited by the minimum lithographic resolution. The vertical Ldd processing was also developed to improve the short channel effects. The transistor with channel length below 0.1 micrometers has normal characteristics at room temperature, a > 6V Bvdss, and a transconductance with value as high as in the conventional planar transistor of the same channel length.

Citation Download Citation

Kiyoshi Mori "Sub-0.1-μm vertical MOS transistor", Proc. SPIE 3881, Microelectronic Device Technology III, (1 September 1999); https://doi.org/10.1117/12.360569

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