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Given the successful development in actinic pattern mask inspection (APMI), high-volume manufacturing of advanced chips including N5 and N3 was realized due to the defect-free masks provided by the TSMC mask shop. This achievement was attributed to the newly developed EUV source and GPU-based defect detection with machine learning (ML) assistance. Unlike conventional approaches which sustain less than two weeks, the rotated crucible fed by Sn fuel in the LPP (Laser-produced plasma) system provided one month of operating stability with ultra-low tin consumption. The newly developed LPP EUV light source has been moved towards double IR power to produce higher EUV photon counts, resulting in better throughput and inspection sensitivity. It enables captured images to possess an effective signalto-noise ratio (SNR) and reasonable inspection nuisance counts. The common technique challenges, Sn auto-refuel and debris mitigation, were overcome by auto-refuel and reuse, debris mitigation, and plasma position control. Moreover, the LPP system also showed its capability in performing pellicle inspection to prolong mask operation periods in wafer foundries. For the GPU-based inspection system, it provided the feasibility and flexibility in algorithm development compared to the FPGA approach. The TSMC developed machine-learning (ML) based rendering model played a key role in aligning features with tool images in D2D mode, as well as residue reduction of D2DB mode. All rendering models were implemented by CUDA coding and running on TSMC-customized GPU architecture to fulfill the goal of high-speed computation and defect capture rate that met production specifications. Combining with the ML model, proper detectors were designed for each specific feature, such as SRAF and curvy OPC design, and the performance of auto defect classification (ADC) with the model has been proven. By integrating all the work, it enabled the actinic tools to fulfill the requirement of massive production significantly.
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