Dr. Yu Yao Chang Profile

Dr. Yu Yao Chang

Senior Engineer at Nanya Technology Corp

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Publications (2)

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Proceedings Article | 20 March 2006 Paper

Model-based OPC for node random size contact hole with SRAF

C. W. Huang, Y. Y. Chang, L. S. Yeh, H. Y. Liao, C. L. Shih, J. P. Lin

Proceedings Volume 6154, 61543C (2006) https://doi.org/10.1117/12.656734

KEYWORDS: Optical proximity correction, SRAF, Model-based design, Photomasks, Data modeling, Scattering, Printing, Manufacturing, Visualization, Error analysis

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One of the most crucial tasks for under 90nm IC is the small contact holes. Traditional model-based OPC is not effective and doesn't cover the process window regarding side-lobe at all. Although there are some novel approaches which have shown good performances, most of them focus on single size contact hole. Actually, there are much more challenges and difficulties to be implanted them on random size contact holes which have various hole sizes in such high 2-D MEEF condition. In consideration of manufacturability, the combination of off-axis, high NA and sub resolution assist features (SRAFs) is still the better candidate to improve process window of contact hole at 65nm generation. But, even that, the implementation of OPC of this combination still needs new concepts and methodologies involved. The reason is that both of random sizes and arbitrary locations really create a lot of difficulties coming from the conflictive placement of SRAFs and side-lobe for various hole sizes and pitches. Moreover, process window of various pitches are strongly affected by SRAFs rules and side-lobe. Therefore, in order to build a more complete OPC model, the OPC model needs special treatment and procedure together with the consideration of design rule and hybrid OPC handling. This study will depict the whole concept and design avoiding the blocks of model-based OPC treatment and build a working flow for OPC SRAF adding.

Proceedings Article | 28 June 2005 Paper

Effects of mask bias on the mask error enhancement factor (MEEF) for low k1 lithography process

Yu Chang, Yuan-Hsun Wu, Chiang-Lin Shih, Jengping Lin, Francis Kan, Jimmy Lin

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617212

KEYWORDS: Photomasks, Critical dimension metrology, Semiconducting wafers, Lithography, Manufacturing, Error analysis, Image quality, Process control, Scanners, Wafer-level optics

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Mask Error Enhancement Factor(MEEF) has recently become an important topic in determining requirements of process. MEEF is the ratio of the CD range on the wafer and the expected CD range due to the mask. It indicates that mask CD errors are in effect magnified during the optical transfer to the wafer. The resolution capability of a optical system is given by Rayleigh’s criterions: Resolution=k1*λ/NA, where λ is the wavelength of the light used and NA is defined as the sine of the maximum half angle(α) of diffracted light which can enter the lens. The k1 resolution-scaling factor (k1=CD*NA/λ) is a practical measure for expressing imaging feasibility of a given optical system. It is a important parameter and direct proportion to resolution requirement. For driving critical CD dimension contraction bellow 0.11μm, lower k1 factor is needed. In this work we use strong OAI (Quasar 90° ) to push k1 reach 0.29 by KrF exposure tool and analysis the MEEF value on 90nm generation. The simulation result shows the predicted MEEF value is close to 9 while using KrF to 90nm resolution and real MEEF value from exposuring Line/Space pattern on wafer data is 6.2. In such high MEEF process, it is very important to control mask CD accuracy. We bring up a test pattern of serial combinations with different Line/Space dimension with the same pitch size to reduce the mask array CD variation. Finally, we compare the process window (PW) between equal and nonequal Line/Space situation. The process window can be improved 18% while line width extends from 90nm to 95nm at fixed pitch 180nm.

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