Implementation of a CMOS digital readout integrated circuit (DROIC) based on pixel level digital time delay integration (TDI) for scanning type LWIR focal plane arrays (FPAs) is presented. TDI is implemented on 8 pixels with over sampling rate of 3. Analog signal integrated on integration capacitor is converted to digital domain in pixel, and digital data is transferred to TDI summation counters, where contributions of 8 pixels are added. Output data is 16 bit, where 8 bits are allocated for most significant bits and 8 bits for least significant bits. Control block of the ROIC, which is responsible of generating timing diagram for switches controlling the pixels and summation counters, is realized with VerilogHDL. Summation counters and parallel-to-serial converter to convert 16 bit parallel output data to single bit output are also realized with Verilog HDL. Synthesized verilog netlists are placed&routed and combined with analog under-pixel part of the design. Quantization noise of analog-to-digital conversion is less than 500e-. Since analog signal is converted to digital domain in-pixel, inaccuracies due to analog signal routing over large chip area is eliminated. ROIC is fabricated with 0.18μm CMOS process and chip area is 10mm2. Post-layout simulation results of the implemented design are presented. ROIC is programmable through serial or parallel interface. Input referred noise of ROIC is less than 750 rms electron, while power consumption is less than 30mW. ROIC is designed to perform in cryogenic temperatures.
KEYWORDS: Short wave infrared radiation, Sensors, Infrared imaging, Signal to noise ratio, Infrared radiation, Staring arrays, Readout integrated circuits, High dynamic range imaging, Analog electronics, Capacitors
This paper presents novel unit cell architecture for short wave infrared (SWIR) imaging applications. It has two input stages which are CTIA and SFD covering for both respectively low and high light, levels and automatic input stage selection circuitry that chooses best input stage. User can select 2 modes for FPA manual and automatic mode. In manual mode, user can set CTIA or SFD for all pixels according to user needs. In automatic mode, each pixel selects input stage itself according to light level. Light level threshold can be adjusted with reference voltage. Automatic input stage selection for each pixel brings high SNR level and low noise along with highest possible dynamic range for SWIR imaging applications. CMOS 0.18μm technology is used to realize unit cell. In the architecture of unit cell, circuit level techniques are used to optimize layout size.
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