KEYWORDS: Transistors, Device simulation, Back end of line, TCAD, Standards development, Process modeling, Performance modeling, Oscillators, New and emerging technologies, Multilayers
Technology evaluation of new nodes is becoming increasingly complex; where transistor performance was once the critical metric, technology evaluation currently requires more complex metrics such as AC power and area. We present a method to utilize Synopsys TCAD to generate HSPICE collateral from device and process simulation to enable circuit simulation. This workflow is automated to support generation of packaged standard cell library collateral, enabling early analysis of more complex circuits which utilize automated routing tools to create. This workflow enables a much more accurate and complete picture of technology performance in a faster way than traditional PDK-based workflows.
Power delivery represents a key challenge in scaled technology nodes as interconnect wiring resistance increases and design constraints impact how much wiring can be used for power distribution. Here, we discuss several methodologies, including both pre-PDK and post-PDK, to benchmark the integrity of power delivery network designs with advanced technology features such as vertical FET (VTFET) transistor architecture, skip-level vias, buried power rails and backside power delivery. For a post-2nm node VTFET architecture, we employ a pre-PDK benchmarking to find that buried power rails can reduce gate delay by as much as 30%. For 5nm and 2nm technology nodes, we use existing PDKs to simulate backside power delivery networks (BS-PDN) and find that scaled logic area can be reduced by 10-30% while minimum-pitch interconnect RC delay can be reduced by as much as 70% depending on reference design.
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