This paper presents a feasibility study on patterning the critical layers of Bit-Line Periphery (BLP) and Storage Node Landing Pad (SNLP) for advanced 10nm node DRAM with sub-40nm pitch using a single EUV patterning. Source Mask Optimization (SMO) and aerial image-based Optical Proximity Correction (OPC) were initially conducted to classify image data and identify potential weak points of the primary patterning mask. A secondary patterning mask was then produced based on the resist model and design split using the obtained data on the primary mask to address these issues. Results obtained through PV-band and intensity analysis of each area in simulation, as well as ADI and AEI (After Etch Inspection) using photoresists with 2 kinds of different tones (PTD CAR and Spin-on MOR PR), demonstrated the feasibility of patterning BLP and SNLP with a single EUV mask. Additionally, Process Window Discovery (PWD) wafers were fabricated to analyze and review process margins and potential weak points through KLA inspection for systematic patterning defectivity. Furthermore, our experiments confirmed that the performance of EUV patterning with DRAM BLP/SNLP layer can be expected to improve by reducing the dose (in mJ/cm2) by approximately 30% using a secondary mask by retarget bias split and resist model OPC.
As the industry continues to scale DRAM cell size, EUV lithography techniques have been considered in one or multiple steps. We have explored a single mask solution to pattern the bit-line-periphery (BLP) and the storage node landing pad (SNLP). Normally, for such varied types of structures as honeycomb arrays, SWD, S/A and Core, multiple masks are required. In this paper, we have explored a single EUV mask approach. First, a freeform EUV light source (in the source mask optimization, or SMO, process) was generated targeting a 36nm pitch honeycomb array and BLP structures. Then, curvilinear optical proximity correction (OPC) was applied to the target design (as shown in Figure 1) such that the performance meets qualified process window variation bands (PVBs) with proper curvilinear mask rule check (MRC). It is important to note that only an optical model was used for SMO and OPC without a resist model in this task. For the wafer process, we have used a dark field mask and metal oxide resist (MOR) photoresist and negative tone development (NTD). This was followed by transferring the pattern into a suitable hardmask for optical defect characterization using the KLA broadband plasma (BBP) 29xx tool as shown in Figure 2. Process window characterization was done to discover a unified defect-free window for both honeycomb array and BLP structures.
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