Comprehensive through-silicon-via (TSV) characterization, including grind side measurements, is critical to ensure device reliability in chiplet technology. Here we report on TSV metrology using spectral interferometry (SI), which is used to acquire absolute phase information of polarized and broad-band light interacting with a sample. This phase information can be translated into the optical path length of the partial beams traveling within the structure. We utilize the spatial separation of peaks related to light reflected from the top surface and the surface of interest to directly measure the TSV depth after reactive ion etching as well as the reveal height on the grind side, without modeling and even in the presence of multilayers or surrounding patterning. Polarization-dependent SI measurements enable the quantification of asymmetry at the bottom of the TSVs not visible in top-down CD measurements. SI is robust and fast and unveils novel information in TSV metrology not accessible with established in-line metrology techniques.
A comprehensive picture of the stress evolution within arrays of through-silicon-vias (TSV) is developed using in-line Raman spectroscopy. A set of wafers with different TSV geometries and metal seed liner thicknesses is exposed to various annealing conditions. Monitoring the Si-Si phonon mode shift between the vias, the influence of via geometries and processing conditions on the stress in the Si substrate is characterized non-destructively. Compressive stress is found in close proximity to the TSVs post Cu fill, as expected. However, for arrays with small TSV pitches, the substrate does not fully relax in the space between the vias, but rather tensile stress accumulates within the arrays. This inter-via stress increases with decreasing TSV pitch, accumulates towards the center of the arrays, and strongly depends on the annealing conditions. High resolution Raman maps within the arrays reveal the full picture of stress distribution in the TSV arrays. By using different excitation wavelengths, the variation of the stress with depth in the Si wafer is probed. The findings demonstrate the value of in-line access to process-dependent stress information. This knowledge helps to define design ground rules for highest device performance or to maximize the useable area on the wafer for logic devices.
A methodology of obtaining the local critical dimension uniformity of contact hole arrays by using optical scatterometry in conjunction with machine learning algorithms is presented and discussed. Staggered contact hole arrays at 44 nm pitch were created by EUV lithography using three different positive-tone chemically amplified resists. To introduce local critical dimension uniformity variations different exposure conditions for dose and focus were used. Optical scatterometry spectra were acquired post development as well as post etch into a SiN layer. Reference data for the machine learning algorithm were collected by critical dimension scanning electron microscopy (CDSEM). The machine learning algorithm was then trained using the optical spectra and the corresponding calculated LCDU values from CDSEM image analyses. It was found that LCDU and CD can be accurately measured with the proposed methodology both post lithography and post etch. Additionally, since the collection of optical spectra post development is non-destructive, same area measurements are possible to single out etch improvements. This optical metrology technique can be readily implemented inline and significantly improves the throughput compared to currently used electron beam measurements.
KEYWORDS: Scatterometry, Back end of line, Metrology, 3D metrology, 3D modeling, Dielectrics, Copper, Process control, Etching, Semiconducting wafers, Photomasks
Scaling of interconnect design rules in advanced nodes has been accompanied by a reducing metrology budget for BEOL process control. Traditional inline optical metrology measurements of BEOL processes rely on 1-dimensional (1D) film pads to characterize film thickness. Such pads are designed on the assumption that solid copper blocks from previous metallization layers prevent any light from penetrating through the copper, thus simplifying the effective film stack for the 1D optical model. However, the reduction of the copper thickness in each metallization layer and CMP dishing effects within the pad, have introduced undesired noise in the measurement. To resolve this challenge and to measure structures that are more representative of product, scatterometry has been proposed as an alternative measurement. Scatterometry is a diffraction based optical measurement technique using Rigorous Coupled Wave Analysis (RCWA), where light diffracted from a periodic structure is used to characterize the profile. Scatterometry measurements on 3D structures have been shown to demonstrate strong correlation to electrical resistance parameters for BEOL Etch and CMP processes. However, there is significant modeling complexity in such 3D scatterometry models, in particlar due to complexity of front-end-of-line (FEOL) and middle-of-line (MOL) structures. The accompanying measurement noise associated with such structures can contribute significant measurement error. To address the measurement noise of the 3D structures and the impact of incoming process variation, a hybrid scatterometry technique is proposed that utilizes key information from the structure to significantly reduce the measurement uncertainty of the scatterometry measurement. Hybrid metrology combines measurements from two or more metrology techniques to enable or improve the measurement of a critical parameter. In this work, the hybrid scatterometry technique is evaluated for 7nm and 14nm node BEOL measurements of interlayer dielectric (ILD) thickness, hard mask thickness and dielectric trench etch in complex 3D structures. The data obtained from the hybrid scatterometry technique demonstrates stable measurement precision, improved within wafer and wafer to wafer range, robustness in cases where 3D scatterometry measurements incur undesired shifts in the measurements, accuracy as compared to TEM and correlation to process deposition time. Process capability indicator comparisons also demonstrate improvement as compared to conventional scatterometry measurements. The results validate the suitability of the method for monitoring of production BEOL processes.
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