The current trend in embedded vision systems is to propose bespoke solutions for specific problems as each application
has different requirement and constraints. There is no widely used model or benchmark which aims to facilitate generic
solutions in embedded vision systems. Providing such model is a challenging task due to the wide number of use cases,
environmental factors, and available technologies. However, common characteristics can be identified to propose an
abstract model. Indeed, the majority of vision applications focus on the detection, analysis and recognition of objects.
These tasks can be reduced to vision functions which can be used to characterize the vision systems. In this paper, we
present the results of a thorough analysis of a large number of different types of vision systems. This analysis led us to
the development of a system’s taxonomy, in which a number of vision functions as well as their combination
characterize embedded vision systems. To illustrate the use of this taxonomy, we have tested it against a real vision
system that detects magnetic particles in a flowing liquid to predict and avoid critical machinery failure. The proposed
taxonomy is evaluated by using a quantitative parameter which shows that it covers 95 percent of the investigated vision
systems and its flow is ordered for 60 percent systems. This taxonomy will serve as a tool for classification and
comparison of systems and will enable the researchers to propose generic and efficient solutions for same class of
systems.
FPGA technology enjoys both the high performance of a dedicated hardware solution and the flexibility of software that is offered by its inherent reprogrammability feature. Image Processing is one application area that can benefit greatly from FPGAs performance and flexibility. This paper presents the design and implementation of a high-level reconfigurable image coprocessor on FPGAs using the Handel-C hardware language. The latter allows non hardware specialists to program FPGAs at a high level using a C-like syntax, albeit with hardware architectures in mind. It hence allows for rapid development of FPGA applications. This is illustrated in this paper in the case of an image coprocessor whose instruction set is based on the operators of Image Algebra. Central to this instruction set are the five core neighbourhood operations of Image Algebra: Convolution, Additive Maximum, Additive Minimum, Multiplicative Maximum and Multiplicative Minimum. These are parameterised in terms of the neighbourhood operation’s window coefficients, window size and image size. Handel-C language was used to design the Image Coprocessor with a fully tested prototype on Celoxica Virtex-E based RC1000-PP PCI board. The paper presents an overview of the approach used to generate FPGA architectures dynamically for the Image Coprocessor using Handel-C, as well as a sample of implementation results.
This paper proposes an integrated framework for the high level design of high performance signal processing algorithms' implementations on FPGAs. The framework emerged from a constant need to rapidly implement increasingly complicated algorithms on FPGAs while maintaining the high performance needed in many real time digital signal processing applications. This is particularly important for application developers who often rely on iterative and interactive development methodologies.
The central idea behind the proposed framework is to dynamically integrate high performance structural hardware description languages with higher level hardware languages in other to help satisfy the dual requirement of high level design and high performance implementation. The paper illustrates this by integrating two environments: Celoxica's Handel-C language, and HIDE, a structural hardware environment developed at the Queen's University of Belfast. On the one hand, Handel-C has been proven to be very useful in the rapid design and prototyping of FPGA circuits, especially control intensive ones. On the other hand, HIDE, has been used extensively, and successfully, in the generation of highly optimised parameterisable FPGA cores. In this paper, this is illustrated in the construction of a scalable and fully parameterisable core for image algebra's five core neighbourhood operations, where fully floorplanned efficient FPGA configurations, in the form of EDIF netlists, are generated automatically for instances of the core. In the proposed combined framework, highly optimised data paths are invoked dynamically from within Handel-C, and are synthesized using HIDE. Although the idea might seem simple prima facie, it could have serious implications on the design of future generations of hardware description languages.
This paper presents an Image Processing Coprocessor implementation for XC6000 series FPGAs. The FPGA acts as a semi-autonomous abstract coprocessor carrying out image processing operational independently. This paper outlines the main structure of the image processing coprocessor in addition to its high level programming environment. The environment provides a library of very high level, parametrized architecture descriptions which are scaleable and general.
Connected Component Labelling is an important task in intermediate image processing. Several algorithms have been developed to handle this problem. Hardware implementations have typically been based on massively parallel architectures, with one logical processing element per pixel. This approach requires a great deal of logic, so current solutions are often implemented in VLSI rather than on FPGAs, and are limited in the size of image which can be labelled.
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