Full fabrication process of nanoscale vacuum channel and gate-all-around nanowire transistors at the 45, 32 and 22 nm technology nodes was simulated in Silvaco TCAD. Comparative analysis of operation modes was made on the basis of the obtained structures. It was shown that nanoscale gate-all-around transistor has sufficiently low power consumption while vacuum channel field effect transistor makes it possible to achieve performance that exceeds performance which can be obtained from the transistor with semiconductor channel. The combination of the above technologies can serve as approach to the creation of low-power and high-speed nanoscale vacuum devices using established complementary metal-oxide-semiconductor (CMOS) technology.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.