Many digital background calibration techniques exist which correct for offset, gain, timing and bandwidth mismatches in time-interleaved (TI) ADCs. Some require an additional reference channel, whereas others are blind and rely on the presence of a band where no signal is present (usually around the Nyquist frequency) or exploit other properties of the input signal. Blind calibration techniques, which don’t use a reference channel, are suitable for correction of commercial TI-ADCs, or TI-ADC systems using commercial ADCs as channels. Techniques employing additional channels require a more complex layout (especially for the clock tree) and need an additional ADC, whose overhead cost is significant, especially for 2- or 4- channel TI-ADCs. However, we show that the estimation process is faster and more accurate when a reference channel is present, and many different error models can be used (exploiting different points in the accuracy / complexity trade-off).
In this paper we present a methodology to calibrate and correct frequency-dependent errors in phased-array antennas with large signal bandwidth and large size. If the receivers are not narrow-band, the hypotheses of constant gain and group delay are not valid. If the frequency responses of the receivers are affected by mismatches, this will also impact directivity. Standard Amplitude and Phase Correction (APC) algorithms will not be effective in this case, and a more advanced complex FIR filtering algorithm is used. A transmitted signal is assumed to be known in order to provide a reference and estimate the optimal calibration coefficients of the FIR filters.
In this paper we propose a model of noisy oscillator to describe the effects of white noise sources on amplitude and phase noise spectrum that can be applied to linear and non-linear structures. This work proposes an extension of previous works to take into account deeper considerations about Analytical Signal and Averaging methodologies to extract a new model for oscillator dynamics.
The Noisy Oscillator model has shown an excellent agreement to literature works, and results obtained with the proposed model have been compared to simulations performed with SpectreRF in Cadence 4.4.3 on a LC oscillator, in order to provide model validation.
Phase noise models that describe the near-carrier spectrum in an accurate but insightful way are needed, to better optimize the oscillator design. In this paper we present a model to describe the effect of flicker noise sources on the phase noise of an oscillator, that can be applied both to linear oscillators and to nonlinear structures like relaxation and ring oscillators, so extending previous works that considered only the effect of the flicker noise superimposed to the control voltage of a VCO. In the phase noise of an oscillator we can separate the effect of high frequency noise sources, that can be described by a short-time-constant system, and the effect of low frequency noises (mostly flicker sources), described by a system with time constants much slower than the oscillation period. Flicker noise has been considered to cause a change in the circuit bias point; this bias point change can be mapped in a shift of the oscillation frequency by exploiting Barkhausen conditions (for linear oscillators) or obtaining this link by simulations. The power spectral density of the oscillator can then be obtained as the probability distribution of the oscillation frequency, starting from the flicker noise probability distribution. If the effect of high frequency noise sources is also taken into account, the overall oscillator spectrum can be obtained as a convolution of the spectrum due to flicker sources with the Lorentzian-shaped spectrum due to white noise sources, in analogy with the description of inhomogeneous broadening of laser linewidth.
A monolithic Clock and Data Recovery (CDR) circuit for SDH STM-16 (2.5 Gb/s) digital receivers has been designed and fabricated using Maxim GST-2 27 GHz Silicon bipolar technology. The main functions carried out by the IC are: signal amplification (40 dB) and limitation, clock recovery and decision. The design is intended to achieve a complete 2.5 Gb/s receiver by using the IC and a low noise preamplifier (transimpedance stage), mounted in a DIL package. The integrated circuit comprises about 400 active devices, used both for analog and digital blocks, and uses two supply voltages of 5 and -4.5 V. The input port is decoupled by external capacitors and matched to 50 (Omega) using on-chip resistors, whereas clock and data outputs are open collector type. The die size is 2 X 2 mm2 and the chip has been packaged using a TQFP 48 pins plastic package. Measurements under 231-1 PRBS data stream have shown an input sensitivity below 5 mVpp, rms output jitter below 7 ps and total power consumption of 0.8 W.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.