The study of the selectivity of the plasma etching of functional materials with respect to the mask of a negative electron resist based on hydrogen-silsesquioxane (HSQ) has been carried out. The formation of nanostructures with sub-50 nm critical dimensions by the HSQ mask has been studied for a number of materials: single-crystal silicon, a metallic Ta layer, dielectric layers of SiO2, Al2O3, HfO2, Si3N4, as well as a porous low-k dielectric based on organosilicate glass (OSG) on silicon substrates. It has been found that HSQ resist masks can be used to manufacture prototypes of microand nanoelectronic devices with critical dimensions less than 10 nanometers using a large number of materials, including for creating structures with relatively high aspect ratios with an absolute thickness of layers of functional materials of tens of nanometers.
The modern IC process consists of a 13-layer metallization stack. Critical dimensions are 30-40 nm at the M0-
M2 metal layers and due to barrier resistance and electromigration reasons, copper is not the perfect choice
nowadays. There are two main alternatives to copper on M0-M2 layers: cobalt and ruthenium. Return to the
subtractive scheme could be a powerful solution for future interconnects although the dry etching process of
the metal is required for it. In this paper, different approaches to plasma etching of cobalt are studied. CO- and
halogen-containing plasmas were considered. It seems that etching in CO-based plasma is inefficient. The rate
was only 2 nm/min in a wide temperature range. The low-temperature (60°C) process of the cobalt etching in
BCl3/Ar plasma was developed. The etching rate for the process was 50 nm/min. All of the considered
processes are found to be aggressive toward the mask.
The fabrication of silicon nanostructures for microelectronic applications is of great interest. We employed two-stage technology of precise anizotropic plasma etching of silicon over e-beam resist and isotropic removal of thermally oxidised defected surface layer of silicon by wet etch to fabricate planar silicon nanowire arrays. Silicon nanowires with diameter of 10-30 nm were obtained. It is simple to get nanowires without oxide or covered with thermal SiO2. Conductivity of obtained silicon nanowire arrays before and after oxidation was measured. It was found that after oxidation and removal of oxide layer conductivity increases dramatically.
The results presented on Silicon one-dimensional structures fabrication which are promising for application in nanoelectronics, sensors, THz-applications. We employ two-stage technology of precise anizotropic plasma etching of silicon over e-beam resist and isotropic removal of thermally oxidised defected surface layer of silicon by wet etch. As first the process for nano-fins fabrication on SOI substrate was developed. HSQ resist was used as a negative-tone electron beam resist with good etch-resistance, high resolution and high mechanical stability. The etching was performed by RIE in mix of SF6 + C4F8. plasma. By changing the ratio SF6:C4F8, the sidewall profile angle can be controlled thoroughly. Next step to minimize lateral size of structures and reduce impact of surface defects on electron mobility in core of nanowires was the application of surface thermal oxidation to defected layer. It was used for selective removal of damaged silicon layer and polymer residues. Oxidation was performed with controlled flow of dry oxygen and water vapour. Oxidation rate was precisely controlled by ex-situ spectral ellipsometry on unpatterned chips As a result the arrays of planar sub-20 nm Silicon nanowires with length in the range 200 nm – 500 um were made.
Application variety and huge potential market of RF MEMS switches guarantee relentless research interest to the field. There are lots of different types of MEMS switches. Direct contact MEMS switches are simplifier for integration than capacitive MEMS switches. Lateral technology considerably simplifies the formation process. The objective of this research is to estimate characteristics of the simple direct-contact lateral MEMS switch and to understand the improvement directions.
The MEMS switches were fabricated on the SOI wafers by e-beam lithography, dry etching and wet HF-etching. E-beam lithography and dry etching were used to form the cantilever and electrodes on the buried oxide layer. The structure with two control electrodes was used. IV characteristics were measured by Keithley 4200-SCS. The distance between cantilever and control electrodes was 100 nm.
From the obtained IV characteristics it is clear that the devices switches at about 60 V. High control voltage could be explained by the large distance between cantilever and control electrode, and high rigidity of the cantilever.
Following simulation in COMSOL Multiphysics showed that the control voltage could be decreased to 20-30 V by adding of spring element to the cantilever and device geometry modification.
Ultrathin (1–10 nm) Cu and Au films were prepared on the silicon and quartz substrates by magnetron sputtering at room temperature. We measured the transmission coefficient of the films at a wavelength of 3cm and analyzed a surface morphology of these films. It was shown that the films with thicknesses less than 7.5 nm (Au) and 3 nm (Cu) are almost transparent for microwaves. This effect is explained by quick oxidation of Cu and the complex surface morphology of nanometer thick films. The Au film morphology is evolved with increasing average Au thickness d from hemispherical islands initially (1.0 nm<d<5.0 nm) to partially coalesced worm-like island structures (d=10 nm).
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