Moore's Law in the innovation era

Mark Bohr

doi:10.1117/12.883462

29 March 2011 Moore's Law in the innovation era

Mark Bohr

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Proceedings Volume 7974, Design for Manufacturability through Design-Process Integration V; 797402 (2011) https://doi.org/10.1117/12.883462
Event: SPIE Advanced Lithography, 2011, San Jose, California, United States

Abstract

Traditional transistor scaling methods served our industry well for more than three decades until the early 1990s when leakage current and active power constraints threatened to end the continued improvements provided by Moore's Law. The end of the traditional scaling era ushered in the beginning of the innovation era. Process technology innovations such as strained silicon, high-k metal gate transistors, and copper + low-k interconnects have enabled continued performance improvements for scaled devices. Microprocessor design and architecture innovations such as multi-core designs combined with power gates were significant contributors to improved performance and improved power efficiency. Future computing products demand small form factors and long battery life that can be met through a combination of transistor innovation, System-on-Chip and System-in-Package integration techniques.

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Mark Bohr "Moore's Law in the innovation era", Proc. SPIE 7974, Design for Manufacturability through Design-Process Integration V, 797402 (29 March 2011); https://doi.org/10.1117/12.883462

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