CFET standard-cell design down to 3Track height for node 3nm and below

S. M. Y. Sherazi; J. K. Chae; P. Debacker; L. Matti; D. Verkest; A. Mocuta; R. H. Kim; A. Spessot; A. Dounde; J. Ryckaert

doi:10.1117/12.2514571

20 March 2019 CFET standard-cell design down to 3Track height for node 3nm and below

S. M. Y. Sherazi, J. K. Chae, P. Debacker, L. Matti, D. Verkest, A. Mocuta, R. H. Kim, A. Spessot, A. Dounde, J. Ryckaert

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Proceedings Volume 10962, Design-Process-Technology Co-optimization for Manufacturability XIII; 1096206 (2019) https://doi.org/10.1117/12.2514571
Event: SPIE Advanced Lithography, 2019, San Jose, California, United States

Abstract

Advanced technology nodes are based on nFET and pFET fins, which are fabricated on the same Silicon level of the wafer. However, in a complimentary FET (CFET) technology the nFET and pFET devices are stacked on top of each other [1]. This provides a significant area reduction mainly driven by a simplified transistor terminal access and the removal of the lateral physical separation between the two transistors. The combination of the CFET with buried power rails can reduce the track height of the cells and the elusive 3 Track standard cell is seen to be a possibility.

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Citation Download Citation

S. M. Y. Sherazi, J. K. Chae, P. Debacker, L. Matti, D. Verkest, A. Mocuta, R. H. Kim, A. Spessot, A. Dounde, and J. Ryckaert "CFET standard-cell design down to 3Track height for node 3nm and below", Proc. SPIE 10962, Design-Process-Technology Co-optimization for Manufacturability XIII, 1096206 (20 March 2019); https://doi.org/10.1117/12.2514571

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