Next-generation logic design architecture for vertical-transport nanosheets

B. Senapati; J. Do; A. Young; D. J. Dechene; S, Song; Y. Park; J. Kong; N. Lanzillo; C. Zhang; S. Fan; S. Baek; S. Mukesh; H. Jagannathan; B. Anderson; T. Wu; D. Guo; K.-I. Seo; H. Bu

doi:10.1117/12.2658187

28 April 2023 Next-generation logic design architecture for vertical-transport nanosheets

B. Senapati, J. Do, A. Young, D. J. Dechene, S, Song, Y. Park, J. Kong, N. Lanzillo, C. Zhang, S. Fan, S. Baek, S. Mukesh, H. Jagannathan, B. Anderson, T. Wu, D. Guo, K.-I. Seo, H. Bu

Author Affiliations +

Proceedings Volume 12495, DTCO and Computational Patterning II; 124950L (2023) https://doi.org/10.1117/12.2658187
Event: SPIE Advanced Lithography + Patterning, 2023, San Jose, California, United States

Abstract

Vertical-Transport (VTFET) Nanosheet Technology is an attractive solution to enable aggressive CMOS scaling in the sub-45nm contact-gate-pitch (CGP) regime. By decoupling the classic tradeoff of S/D contacts, gate length & contact-gate-pitch (CGP), VTFET technology overcomes middle-of-the-line (MOL) dominated performance pinch-points by providing independent optimization of the contact dimension & device width as well as significant effective capacitance (Ceff) reduction [1]. VTFET offers an attractive solution at sub-45nm CGP, however it introduces unique design challenges that need to be optimized to take full power-performance-area (PPA) entitlement. In this paper, we present for the first time a logic standard cell architecture to enable a competitive VTFET technology. First, we introduce key features of the VTFET architecture which enable significant advantages relative to leading-edge competitive technologies. Further we describe key Design Technology Co-Optimization (DTCO) scaling knobs that naturally lend themselves to VTFET such as single fins, buried power rails and gate-contact super vias can achieve competitive area scaling vs. an industry 7nm lateral FinFET transistor reference. Finally, we draw conclusions of overall PPA benefits of this technology.

Conference Presentation

Citation Download Citation

B. Senapati, J. Do, A. Young, D. J. Dechene, S, Song, Y. Park, J. Kong, N. Lanzillo, C. Zhang, S. Fan, S. Baek, S. Mukesh, H. Jagannathan, B. Anderson, T. Wu, D. Guo, K.-I. Seo, and H. Bu "Next-generation logic design architecture for vertical-transport nanosheets", Proc. SPIE 12495, DTCO and Computational Patterning II, 124950L (28 April 2023); https://doi.org/10.1117/12.2658187

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