EUV lithography for 22nm half pitch and beyond: exploring resolution, LWR, and sensitivity tradeoffs

E. Steve Putna; Todd R. Younkin; Roman Caudillo; Manish Chandhok

doi:10.1117/12.842408

20 March 2010 EUV lithography for 22nm half pitch and beyond: exploring resolution, LWR, and sensitivity tradeoffs

E. Steve Putna, Todd R. Younkin, Roman Caudillo, Manish Chandhok

Proceedings Volume 7636, Extreme Ultraviolet (EUV) Lithography; 76360P (2010) https://doi.org/10.1117/12.842408
Event: SPIE Advanced Lithography, 2010, San Jose, California, United States

Abstract

The International Technology Roadmap for Semiconductors (ITRS) denotes Extreme Ultraviolet (EUV) lithography as a leading technology option for realizing the 22nm half pitch node and beyond. Readiness of EUV materials is currently one high risk area according to recent assessments made at the 2009 EUVL Symposium. The main development issue regarding EUV resist has been how to simultaneously achieve high sensitivity, high resolution, and low line width roughness (LWR). This paper describes the strategy and current status of EUV resist development at Intel Corporation. Data collected utilizing Intel's Micro-Exposure Tool (MET) is presented in order to examine the feasibility of establishing a resist process that simultaneously exhibits ≤22nm half-pitch (HP) L/S resolution at ≤ 12.5mJ/cm² with ≤ 4nm LWR.

Citation Download Citation

E. Steve Putna, Todd R. Younkin, Roman Caudillo, and Manish Chandhok "EUV lithography for 22nm half pitch and beyond: exploring resolution, LWR, and sensitivity tradeoffs", Proc. SPIE 7636, Extreme Ultraviolet (EUV) Lithography, 76360P (20 March 2010); https://doi.org/10.1117/12.842408

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