Modification of existing chip layout for yield and reliability improvement by computer-aided design tools

Mu-Jing Li; Suryanarayana Maturi; Pankaj Dixit

doi:10.1117/12.504322

10 July 2003 Modification of existing chip layout for yield and reliability improvement by computer-aided design tools

Mu-Jing Li, Suryanarayana Maturi, Pankaj Dixit

Proceedings Volume 5042, Design and Process Integration for Microelectronic Manufacturing; (2003) https://doi.org/10.1117/12.504322
Event: Advanced Microelectronic Manufacturing, 2003, Santa Clara, CA, United States

Abstract

A CAD flow has been developed to modify an existing large scale chip layout to reinforce the redundant via design rules to improve the yield and reliability. The flow operates on each metal-via pair from bottom up to correct the redundant via rule violations. It divides a large complex design into cells, so that multiple process can work concurrently as if every process were working on the top level to reach the goal in a reasonable time.

Citation Download Citation

Mu-Jing Li, Suryanarayana Maturi, and Pankaj Dixit "Modification of existing chip layout for yield and reliability improvement by computer-aided design tools", Proc. SPIE 5042, Design and Process Integration for Microelectronic Manufacturing, (10 July 2003); https://doi.org/10.1117/12.504322

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