Low-power high-speed threshold logic and its application to the design of novel carry lookahead adders

Peter Celinski; Jose Fco. Lopez; Said F. Al-Sarawi; Derek Abbott

doi:10.1117/12.449155

21 November 2001 Low-power high-speed threshold logic and its application to the design of novel carry lookahead adders

Peter Celinski, Jose Fco. Lopez, Said F. Al-Sarawi, Derek Abbott

Proceedings Volume 4591, Electronics and Structures for MEMS II; (2001) https://doi.org/10.1117/12.449155
Event: International Symposium on Microelectronics and MEMS, 2001, Adelaide, Australia

Abstract

The first main result of this paper is the development of a low power threshold logic gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have very low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. The second main result is the development of a novel, low depth, carry look ahead addition scheme. One such adder is also designed using the proposed gate.

Citation Download Citation

Peter Celinski, Jose Fco. Lopez, Said F. Al-Sarawi, and Derek Abbott "Low-power high-speed threshold logic and its application to the design of novel carry lookahead adders", Proc. SPIE 4591, Electronics and Structures for MEMS II, (21 November 2001); https://doi.org/10.1117/12.449155

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