Development of GaAs JFETs for cryogenic electronic circuits

Kenichi Okumura; Iwao Hosako; Yukari Yamashita-Yui; Makoto Akiba; Norihisa Hiromoto

doi:10.1117/12.317307

21 August 1998 Development of GaAs JFETs for cryogenic electronic circuits

Kenichi Okumura, Iwao Hosako, Yukari Yamashita-Yui, Makoto Akiba, Norihisa Hiromoto

Proceedings Volume 3354, Infrared Astronomical Instrumentation; (1998) https://doi.org/10.1117/12.317307
Event: Astronomical Telescopes and Instrumentation, 1998, Kona, HI, United States

Abstract

GaAs JFET with various gate sizes, which ranges from 0.5 to 200 micrometers in gate length and from 2 to 200 micrometers in gate width, are fabricated and their DC characteristics and low- frequency noise spectra are measured at low temperatures in order to develop cryogenic electronic circuits for a far-IR detector array on board a satellite such as the Japanese IR satellite. We obtained the following results from the noise measurements: (1) Noise spectra of GaAs JFETs are dominated by a 1/f noise and include some generation-recombination noises in low-frequencies. (2) The 1/f noise voltage is found to remarkably depend on both the gate length and the drain-source voltage, but the gate width and the gate-source voltage have not almost concern with the 1/f noise voltage. Therefore, we suppose that the electric field in the channel of the GaAs JFET mainly contributes to the 1/f noise. By using these characteristics, the GaAs JFET having very low power dissipation and very low noise will be designed for cryogenic readout circuits at low temperatures.

Citation Download Citation

Kenichi Okumura, Iwao Hosako, Yukari Yamashita-Yui, Makoto Akiba, and Norihisa Hiromoto "Development of GaAs JFETs for cryogenic electronic circuits", Proc. SPIE 3354, Infrared Astronomical Instrumentation, (21 August 1998); https://doi.org/10.1117/12.317307

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