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1 May 1994 Signal processing techniques for defect inspection of distorted patterned wafers
Babak H. Khalaj, Hamid K. Aghajan, Arogyaswami Paulraj, Thomas Kailath
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Proceedings Volume 2196, Integrated Circuit Metrology, Inspection, and Process Control VIII; (1994) https://doi.org/10.1117/12.174154
Event: SPIE's 1994 Symposium on Microlithography, 1994, San Jose, CA, United States
Abstract
A self-reference technique is developed for detecting the location of defects in repeated pattern wafers and masks with low-order distortions. If the patterns are located on a perfect rectangular grid, it is possible to estimate the period of repeated patterns in both directions and then produce a defect-free reference image for making comparison with the actual image. But in some applications, the repeated patterns are somehow shifted from their desired position on a rectangular grid, and the aforementioned algorithm can not be directly applied. In these situations, to produce a defect-free reference image and locate the defected cells, it is necessary to estimate the amount of misalignment of each cell beforehand. The proposed technique first estimates the misalignment of repeated patterns in each row and column. After estimating the location of all cells in the image, a defect-free reference image is generated by averaging over all the cells and is compared with the input image to localize the possible defects.
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Babak H. Khalaj, Hamid K. Aghajan, Arogyaswami Paulraj, and Thomas Kailath "Signal processing techniques for defect inspection of distorted patterned wafers", Proc. SPIE 2196, Integrated Circuit Metrology, Inspection, and Process Control VIII, (1 May 1994); https://doi.org/10.1117/12.174154
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KEYWORDS
Semiconducting wafers
Defect inspection
Signal processing
Detector development
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