Paper
8 October 1998 Minimum multiplicative complexity implementation of the 2D DCT using Xilinx FPGAs
Chris H. Dick
Author Affiliations +
Proceedings Volume 3526, Configurable Computing: Technology and Applications; (1998) https://doi.org/10.1117/12.327032
Event: Photonics East (ISAM, VVDC, IEMB), 1998, Boston, MA, United States
Abstract
This paper investigates two options for the field programmable gate array (FPGA) implementation of a very high-performance 2D discrete cosine transform (DCT) processor for real-time applications. The first architecture exploits the transform separability and uses a row-column decomposition. The row and column processors are realized using distributed arithmetic (DA) techniques. The second approach uses a naturally 2D method based on polynomial transforms. The paper provides an overview of the DCT calculation using DA methods and describes the FPGA implementation. A tutorial overview of a computationally efficient method for computing 2D DCTs using polynomial transforms is presented. A detailed analysis of the datapath for this approach using an 8 X 8 data-set is given. Comparisons are made that show the polynomial transform approach to require 67% of the logic resources of a DA processor for equal throughputs. The polynomial transform approach is also shown to scale better with increasing block size than the DA approach.
© (1998) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.
Chris H. Dick "Minimum multiplicative complexity implementation of the 2D DCT using Xilinx FPGAs", Proc. SPIE 3526, Configurable Computing: Technology and Applications, (8 October 1998); https://doi.org/10.1117/12.327032
Lens.org Logo
CITATIONS
Cited by 6 scholarly publications.
Advertisement
Advertisement
RIGHTS & PERMISSIONS
Get copyright permission  Get copyright permission on Copyright Marketplace
KEYWORDS
Field programmable gate arrays

Logic

Clocks

Image processing

Color image processing

Digital signal processing

Video

RELATED CONTENT

Image processing using reconfigurable FPGAs
Proceedings of SPIE (October 21 1996)
A vector DSP for digital media processing
Proceedings of SPIE (May 07 2003)
FFT on reconfigurable hardware
Proceedings of SPIE (September 19 1995)
Implementation of 2-D DCT based on FPGA
Proceedings of SPIE (August 19 2010)

Back to Top