Mr. Zhengfang Liu Profile

Zhengfang Liu

at Siemens EDA

SPIE Involvement:

Author

Publications (15)

Proceedings Article | 10 December 2024 Paper

Paper

Evaluation of hotspots EPE propagation through step-by-step SEM contour analysis

Kan Zhou, Wenzhan Zhou, Yuanyuan Meng, Xiaohang Su, Libo Wang, Xiaoci Li, Zhengfang Liu, Chunshan Du, Huaiyang Dou

Proceedings Volume 13423, 1342312 (2024) https://doi.org/10.1117/12.3052998

KEYWORDS: Statistical analysis, Visualization, Critical dimension metrology, Contour extraction, Scanning electron microscopy, Metals, Data analysis, Back end of line, Overlay metrology, Electronic design automation

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Proceedings Article | 23 March 2020 Paper

Paper

An efficient way to accelerate litho hotspot checking

Jet Jiang, Gavin Li, Frank Hou, Qijian Wan, Xinyi Hu, Zhengfang Liu, Zhixi Chen, Chunshan Du

Proceedings Volume 11328, 1132818 (2020) https://doi.org/10.1117/12.2551682

KEYWORDS: Lithography, Design for manufacturing, Manufacturing, Computer simulations, Databases

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Proceedings Article | 23 March 2020 Paper

Paper

Explore process weak patterns for manufacturing friendly design

Jet Jiang, Frank Hou, Gavin Li, Marfe Ma, Kuan Hu, Chunshan Du, Qijian Wan, Zhengfang Liu, Xinyi Hu, Elven Huang, Wael ElManhawy

Proceedings Volume 11328, 1132812 (2020) https://doi.org/10.1117/12.2551691

KEYWORDS: Machine learning, Data modeling, Semiconducting wafers, Manufacturing, Silicon, Design for manufacturability, Databases, Data analysis, Neural networks, Roads

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Proceedings Article | 23 March 2020 Paper

Paper

VIA design optimization for fast yield ramping in advanced nodes

Min Wang, Yizhong Zhang, Shirui Yu, Xinyi Hu, Qijian Wan, Zhengfang Liu, Zhixi Chen, Chunshan Du

Proceedings Volume 11328, 1132814 (2020) https://doi.org/10.1117/12.2551683

KEYWORDS: Metals, Design for manufacturing, Manufacturing, Particles, Yield improvement, Design for manufacturability, Roads, Polishing, Photomasks, Integrated circuit design

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Proceedings Article | 23 March 2020 Paper

Paper

CMP simulation-based dummy fill optimization

Liwei Jiang, Yun Cao, Jiao Zhang, Fang Wei, Zhengfang Liu, Chunshan Du, Ruben Ghulghazaryan, Davit Piliposyan, Jeff Wilson, Qijian Wan, Xinyi Hu, Zhixi Chen

Proceedings Volume 11328, 1132817 (2020) https://doi.org/10.1117/12.2551681

KEYWORDS: Chemical mechanical planarization, Manufacturing, Optimization (mathematics), Copper, Design for manufacturing, Lithography, Modeling and simulation, Product engineering, Semiconducting wafers, Model-based design

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Proceedings Article | 23 March 2020 Paper

Paper

A comprehensive standard cell library qualification to prevent lithographic challenges

Xinyi Hu, Qijian Wan, Zhengfang Liu, Zhixi Chen, Chunshan Du

Proceedings Volume 11328, 113281C (2020) https://doi.org/10.1117/12.2551677

KEYWORDS: Lithography, Standards development, Databases, Photomasks, Statistical analysis, Visualization, Roads, Optics manufacturing, Computer simulations, Metals

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Proceedings Article | 20 March 2019 Paper

Paper

FEOL CMP modeling challenges and solution in 3D NAND

Yang Li, Rick Li, Peng Jiang, Luming Fan, Aman Zheng, Sicong Wang, Guangyi Wang, Chunshan Du, Zhengfang Liu, Ruben Ghulghazaryan, Qijian Wan, Xinyi Hu

Proceedings Volume 10962, 1096211 (2019) https://doi.org/10.1117/12.2515167

KEYWORDS: Chemical mechanical planarization, 3D modeling, Data modeling, Front end of line, Calibration, Polishing, Oxides, Manufacturing, Process modeling, Transmission electron microscopy

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Proceedings Article | 20 March 2019 Paper

Paper

Copper interconnect topography simulation in 3D NAND designs

Yang Li, Rick Li, Peng Jiang, Luming Fan, Aman Zheng, Sicong Wang, Guangyi Wang, Zhengfang Liu, Chunshan Du, Ruben Ghulghazaryan, Qijian Wan, Xinyi Hu

Proceedings Volume 10962, 1096210 (2019) https://doi.org/10.1117/12.2515161

KEYWORDS: Chemical mechanical planarization, 3D modeling, Manufacturing, Process modeling, Data modeling, Copper, Semiconducting wafers, Back end of line, Chemical vapor deposition, Design for manufacturability

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Proceedings Article | 20 March 2019 Paper

Paper

An efficient way of automatic layout decomposition and pattern classification

Zhenzhen Wan, Limei Liu, Huan Kan, Qijian Wan, Xinyi Hu, Zhengfang Liu, Chunshan Du

Proceedings Volume 10962, 1096214 (2019) https://doi.org/10.1117/12.2515137

KEYWORDS: Image classification, Library classification systems, Databases, Logic, Metals, Standards development, Front end of line, Back end of line, Design for manufacturing

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Proceedings Article | 20 March 2019 Paper

Paper

A smart litho friendly design method to enable fast lithography hotspots detection in design flow

Xiaolong Ma, Yanxiang Liu, Xinyi Hu, Qijian Wan, Zhengfang Liu, Chunshan Du, Liguo Zhang

Proceedings Volume 10962, 1096215 (2019) https://doi.org/10.1117/12.2515135

KEYWORDS: Lithography, Logic, Image classification, Visualization, Computer simulations, Manufacturing, Roads, Databases, Library classification systems

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Proceedings Article | 20 March 2018 Paper

Paper

Leveraging pattern matching to solve SRAM verification challenges at advanced nodes

Huan Kan, Lucas Huang, Legender Yang, Elaine Zou, Qijian Wan, Chunshan Du, Xinyi Hu, Zhengfang Liu, Yu Zhu, Recoo Zhang, Elven Huang, Jonathan Muirhead

Proceedings Volume 10588, 105880Z (2018) https://doi.org/10.1117/12.2297340

KEYWORDS: Visualization, Multilayers, Manufacturing, Intellectual property

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Proceedings Article | 20 March 2018 Paper

Paper

Using pattern based layout comparison for a quick analysis of design changes

Lucas Huang, Legender Yang, Huan Kan, Elain Zou, Qijian Wan, Chunshan Du, Xinyi Hu, Zhengfang Liu

Proceedings Volume 10588, 105880X (2018) https://doi.org/10.1117/12.2297346

KEYWORDS: Databases, Design for manufacturability, Manufacturing, Failure analysis, Data processing

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A design usually goes through several versions until achieving a most successful one. These changes between versions are not a complete substitution but a continual improvement, either fixing the known issues of its prior versions (engineering change order) or a more optimized design substitution of a portion of the design. On the manufacturing side, process engineers care more about the design pattern changes because any new pattern occurrence may be a killer of the yield. An effective and efficient way to narrow down the diagnosis scope appeals to the engineers. What is the best approach of comparing two layouts? A direct overlay of two layouts may not always work as even though most of the design instances will be kept in the layout from version to version, the actual placements may be different. An alternative way, pattern based layout comparison, comes to play. By expanding this application, it makes it possible to transfer the learning in one cycle to another and accelerate the process of failure analysis.

This paper presents a solution to compare two layouts by using Calibre DRC and Pattern Matching. The key step in this flow is layout decomposition. In theory, with a fixed pattern size, a layout can always be decomposed into limited number of patterns by moving the pattern center around the layout, the number is limited but may be huge if the layout is not processed smartly! A mathematical answer is not what we are looking for but an engineering solution is more desired. Layouts must be decomposed into patterns with physical meaning in a smart way. When a layout is decomposed and patterns are classified, a pattern library with unique patterns inside is created for that layout. After individual pattern libraries for each layout are created, run pattern comparison utility provided by Calibre Pattern Matching to compare the pattern libraries, unique patterns will come out for each layout. This paper illustrates this flow in details and demonstrates the advantage of combining Calibre DRC and Calibre Pattern Matching.

Proceedings Article | 20 March 2018 Paper

Paper

An efficient way of layout processing based on calibre DRC and pattern matching for defects inspection application

Helen Li, Robben Lee, Tyzy Lee, Teddy Xue, Hermes Liu, Hall Wu, Qijian Wan, Chunshan Du, Xinyi Hu, Zhengfang Liu

Proceedings Volume 10588, 105880Y (2018) https://doi.org/10.1117/12.2297349

KEYWORDS: Defect inspection, Inspection equipment, Defect detection, Scanners

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As technology advances, escalating layout design complexity and chip size make defect inspection becomes more challenging than ever before. The YE (Yield Enhancement) engineers are seeking for an efficient strategy to ensure accuracy without suffering running time. A smart way is to set different resolutions for different pattern structures, for examples, logic pattern areas have a higher scan resolution while the dummy areas have a lower resolution, SRAM area may have another different resolution. This can significantly reduce the scan processing time meanwhile the accuracy does not suffer. Due to the limitation of the inspection equipment, the layout must be processed in order to output the Care Area marker in line with the requirement of the equipment, for instance, the marker shapes must be rectangle and the number of the rectangle shapes should be as small as possible. The challenge is how to select the different Care Areas by pattern structures, merge the areas efficiently and then partition them into pieces of rectangle shapes. This paper presents a solution based on Calibre DRC and Pattern Matching. Calibre equation-based DRC is a powerful layout processing engine and Calibre Pattern Matching’s automated visual capture capability enables designers to define these geometries as layout patterns and store them in libraries which can be re-used in multiple design layouts. Pattern Matching simplifies the description of very complex relationships between pattern shapes efficiently and accurately. Pattern matching’s true power is on display when it is integrated with normal DRC deck. In this application of defects inspection, we first run Calibre DRC to get rule based Care Area then use Calibre Pattern Matching’s automated pattern capture capability to capture Care Area shapes which need a higher scan resolution with a tune able pattern halo. In the pattern matching step, when the patterns are matched, a bounding box marker will be output to identify the high resolution area. The equation-based DRC and Pattern Matching effectively work together for different scan phases.

Proceedings Article | 20 March 2018 Paper

Paper

A smart way to identify and extract repeated patterns of a layout

Fang Wei, Tingting Gu, Zhihao Chu, Chenming Zhang, Han Chen, Jun Zhu, Xinyi Hu, Chunshan Du, Qijian Wan, Zhengfang Liu

Proceedings Volume 10588, 105880W (2018) https://doi.org/10.1117/12.2297303

KEYWORDS: Optical proximity correction, Error analysis, Feature extraction, Statistical analysis, Microelectronics, Silicon, Visualization, Integrated circuits, Manufacturing

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As integrated circuits (IC) technology moves forward, manufacturing process is facing more and more challenges. Optical proximity correction (OPC) has been playing an important role in the whole manufacturing process. In the deep sub-micron technology, OPC engineers not only need to guarantee the layout designs to be manufacturable but also take a more precise control of the critical patterns to ensure a high performance circuit. One of the tasks that would like to be performed is the consistency checking as the identical patterns under identical context should have identical OPC results in theory, like SRAM regions. Consistency checking is essentially a technique of repeated patterns identification, extraction and derived patterns (i.e. OPC results) comparison. The layout passing to the OPC team may not have enough design hierarchical information either because the original designs may have undergone several layout processing steps or some other unknown reasons. This paper presents a generic way to identify and extract repeated layout structures in SRAM regions purely based on layout pattern analysis through Calibre Pattern Matching and Calibre equation-based DRC (eqDRC). Without Pattern Matching and eqDRC, it will take lots of effort to manually get it done by trial and error, it is almost impossible to automate the pattern analysis process. Combining Pattern Matching and eqDRC opens a new way to implement this flow. The repeated patterns must have some fundamental features for measurement of pitches in the horizontal and vertical direction separately by Calibre eqDRC and meanwhile can be a helper to generate some anchor points which will be the starting points for Pattern Matching to capture patterns. The informative statistical report from the pattern search tells the match counts individually for each patterns captured. Experiment shows that this is a smart way of identifying and extracting repeated structures effectively. The OPC results are the derived layers on these repeated structures, by running pattern search using design layers as pattern layers and OPC results as marker layers, it is an easy job to compare the consistency.

Proceedings Article | 20 March 2018 Paper

Paper

A weak pattern random creation and scoring method for lithography process tuning

Meili Zhang, Guogui Deng, Mudan Wang, Shirui Yu, Xinyi Hu, Chunshan Du, Qijian Wan, Zhengfang Liu, Gensheng Gao, Aliaa Kabeel, Kareem Madkour, Wael ElManhawy, Joe Kwan

Proceedings Volume 10588, 105880U (2018) https://doi.org/10.1117/12.2297296

KEYWORDS: Lithography, Visualization, Manufacturing, New and emerging technologies, Failure analysis, Multilayers, Logic, Reliability, Analytical research

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Showing 5 of 15 publications

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