This paper presents a high-speed CMOS image sensor whose frame rate exceeds 2000 frames/sec (fps). The pixel includes a photodiode, a charge-transfer amplifier, and circuitry for correlated double sampling (CDS) and global electronic shuttering. Reset noise, which is the major random noise factor, is reduced by the CDS combined with the charge-transfer amplifier. The total number of devices in the pixel is 11 transistors and 2 MOS capacitors. Test circuits were fabricated using the 0.25 um CMOS process. The sensitivity of the 20 x 20 um2 pixel using the floating diffusion capacitor of 6.2 fF and the photodiode area of 15 x 12.7 um^2 is 34 V/lux-sec. At 1000 fps, noise level is 2.43 mVrms (dark). The noise level and the sensitivity are greatly improved compared to the non-charge-transfer pixel without global shutter (3Tr-type) implemented with the same technology, and to a previous version of the APS with in-pixel CDS.
In this paper, we propose 32 parallel image compression circuits for high-speed cameras. The proposed compression circuits are based on a 4 x 4-point 2-dimensional DCT using a DA method, zigzag scanning of 4 blocks of the 2-D DCT coefficients and a 1-dimensional Huffman coding. The compression engine is designed with FPGAs, and the hardware complexity is compared with JPEG algorithm. It is found that the proposed compression circuits require much less hardware, leading to a compact high-speed implementation of the image compression circuits using parallel processing architecture. The PSNR of the reconstructed image using the proposed encoding method is better than that of JPEG at the region of low compression ratio.
This paper presents a high-speed CMOS image sensor of whose frame rate exceeds 2000 frames/s. The pixel includes a photodiode, a charge-transfer amplifier, and circuitry for correlated double sampling (CDS) and global electronic shuttering. Reset noise, which is a major random noise factor, is greatly reduced by the CDS combined with the charge-transfer amplifier. The total number of devices in the pixel is 11 transistors and 2 MOS capacitors. Test circuits were fabricated using a 0.25μm CMOS process. The sensitivity of the 20 x 20μm2 pixel using the floating diffusion capacitor of 6.2fF and the photodiode area of 15 x 12.7μm2 is 34V/lux-sec. At 1000frames/sec, noise level is 2.43mVrms (dark). The noise level and the sensitivity are greatly improved compared with a 3Tr. type APS implemented with the same technology and a previous version of the APS with in-pixel CDS.
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