KEYWORDS: Lithography, Model-based design, Process modeling, Design for manufacturing, Design for manufacturability, Manufacturing, Optics manufacturing, Very large scale integration, Resolution enhancement technologies, Interfaces
This paper presents a model-assisted routing technique for improving lithography robustness of synthesized layouts.
Presupposing an accurate lithography model and a model-based layout weak spot identification procedure,
this method produces routed layout in-situ with acceptable turn around time. The approach starts with a
conventionally routed layout that, although conforming to design rules, may contain undesirable layout configurations
that the router should reconcile. Since weak spot identification is computation intensive, rule-based
filtering is first applied to the incoming layout to select regions for further model-based analysis. The router
then performs a non-discriminate correction to reduce the number of potential weak spots. This reduced set
subsequently undergoes model-based weak spot analysis, distinguishing the actual weak spots. The router finally
optimizes the layout to remove the identified weak spots.
This technique has been implemented in an industry detail router, and tested with 65-nm technology. Experimental
results show that this method can effectively remove actual weak spots with reasonable runtime.
In this paper, we propose a timing-driven floorplanning algorithm for general building block layout. Our basic idea is based on floorplan enumeration and Zero-Slack algorithm. In our system, floorplanning is performed hierarchically followed by an incremental global routing. Whenever a node in cluster tree is floorplanned, all possible floorplan patterns are enumerated and then the floorplan pattern with best timing behavior and area, shape matches is chosen as solution. Due to our work's background, without the cost of limited floorplan patterns in BEAR, we are awarded by good performance and routability. The complexity analysis is presented also.
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