KEYWORDS: Photomasks, Inspection, Extreme ultraviolet, Line width roughness, Signal to noise ratio, Deep ultraviolet, Scanning electron microscopy, Critical dimension metrology, Extreme ultraviolet lithography
Deep Ultra Violet (DUV) inspection of Extreme Ultra Violet (EUV) mask has been known for high stability, high throughput, and low cost, since it has been used for a long time, even though sensitivity is thought to be insufficient for the EUV mask of under 20 nm half pitch (hp). We have been studying extendibility for 1X nm hp of the DUV inspection using optics named Super Inspection Resolution Improvement method for UnreSolved pattern (SIRIUS). In previous study, we demonstrated the DUV inspection has capability for the EUV mask of 17 nm hp Lines and Spaces (LS) on wafer. In this paper, the more extendibility for the DUV inspection of EUV masks under sub-15 nm on wafer was demonstrated by studying relationship of roughness and sensitivity. Firstly, an estimated model for effects of the EUV mask roughness to Signal Noise Ratio (SNR) of the inspection image was established, and simulation was carried out. Secondly, the SNR was evaluated using actual Line Width Roughness (LWR) improved masks. It was confirmed that the results are the same trend as the model and the simulation, and, the SNR is enhanced with the LWR improvement. Finally, the sensitivity of the LWR improved mask was evaluated. As a result, it becomes enough for the EUV mask over 13 nm hp on wafer. In conclusion, we confirm that the DUV inspection of the EUV mask by the SIRIUS can be extending to the 13 nm hp LS on wafer, this is around the limit of NA 0.33 EUV lithography, using the LWR improved mask.
Programmed defect masks (PDMs) of a tantalum-based absorber were fabricated by a conventional and improved process that decreased the mask line width roughness (LWR). The improved mask LWR decreased the minimum size of recognizable defects from 18.6 nm to 10.9 nm. The PDMs were printed on wafers and their defect printabilities were compared. The correlation coefficients of the relationship between the mask defect size and deviation of wafer critical dimension (CD) caused by the defects were calculated. A significance test of the correlation coefficients of the PDMs produced by the conventional and improved process indicated there was no significant difference between them. This means that the mask LWR did not have a significant influence on defect printability.
We report on the reduction of the mask 3D effect in an etched 40-pair multilayer extreme ultraviolet (EUV) lithography mask by measuring the printed ΔCD (horizontal–vertical) on exposure with a high-NA small field exposure tool (HSFET). We compared these patterns with those of a conventional Ta-based absorber EUV lithography mask. Next, we examined the programmed pattern defect printability of the etched 40-pair multilayer EUV lithography mask and showed that defect printability of the etched multilayer mask was hardly influenced by the direction of EUV illumination. We conclude that the mask 3D effect reduction contributes to simple specifications of the mask pattern defect printability in EUV lithography.
With shrinkage of device pattern, optical proximity correction (OPC) will be used for EUV lithography, which leads to need sub resolution assist features (SRAF) on EUV mask. Currently, it is difficult to fabricate EUV mask with SRAF of sub-30nm using conventional resist mask process stably. Moreover, it is necessary to improve line width roughness (LWR) of mask absorber pattern for achieving the lithographic specifications beyond hp15nm patterning. In this paper, in order to meet the requirements of Ta based absorber EUV mask with SRAF, mask fabrication process using new structure blank is studied for sub-30nm SRAF patterning and for improved LWR of primary feature. New mask process using new blank with thinner resist and Cr based hard mask was developed. By using new mask process, resolution of absorber pattern was achieved to 30nm for SRAF patterning, and LWR was improved comparing with conventional process.
Multilayer defects (ML-defects) are the most specific type of defects on a mask for extreme ultraviolet (EUV) lithography. The intent of this paper has been to study the practical limits of the pattern shift technique to cover such defects by the absorber pattern. We have targeted to apply pattern shift to a 16nm half-pitch EUV single exposure, interconnect-like layer, in which absorber features are predominantly as small as 64nm at mask level. Three main contributors to successful defect coverage are the lateral size of the defect, the alignment of the mask pattern to the fiducial marks and the location accuracy of the blank defects relative to these fiducial marks. For our experimental analysis, we have used a specific approach in which, rather than explicitly targeting to cover the defects to render them non-printing, we kept the possibility to study their printability, together with the possibility to assess the achieved alignment of the mask pattern to the defectivity map of the blank. This was achieved by superimposing a dedicated marker frame, with the expected defect position at its center, onto a lines-and-spaces (l/s) pattern with 16nm half-pitch (at wafer scale). The marker frame allows to determine the deviation of the defect position from the expected one, and the printing impact of the defect on the l/s pattern can be compared to its expected behavior based on its relative position within the 32nm period. It is shown that mitigation feasibility is strongly dependent on the accuracy of the defect position information. Our results suggest targeting to improve that.
Printability estimation of blank defects on an extreme ultraviolet (EUV) mask was examined by means of actinic darkfield imaging. A dedicated mask containing 64-nm line and space pattern was fabricated on a blank with known native blank defects. Actinic dark-field images of the defects on the patterned mask were obtained, and the defect signal intensities through focus were measured. The mask was printed through focus onto a wafer with an ASML NXE3300, and the wafer critical dimension (CD) deviations caused by the defect were obtained. A significant relationship is shown between the defect signal intensity and the wafer CD deviation, corresponding well with simulations. It was thus demonstrated that the wafer CD deviation can be estimated via the defect signal intensity on the mask in the actinic darkfield image.
It is generally said that conventional deep ultraviolet inspection tools have difficulty meeting the defect requirement for extreme ultraviolet masks of hp 1X nm. In previous studies, it has been shown that the newly developed optics and systems using deep ultraviolet, named Super Inspection Resolution Improvement method for UnreSolved pattern (SIRIUS), has high sensitivity for nanoimprint lithography templates with unresolved patterns which are the same scale as the wafer. In this paper, the capability of SIRIUS for the extreme ultraviolet mask of hp 1X nm lines and spaces pattern has been studied by evaluating the signal to noise ratio of inspection images and capture rates with 5 runs to the target defects which cause over 10% printed wafer critical dimension errors calculated by simulation. It was demonstrated that the signal to noise ratio was increased and the all target defects became detectable with the throughput of 120 min per 100 × 100 mm2 . Additionally, the printability of natural defects detected with SIRIUS was analyzed. It was confirmed that SIRIUS was able to detect natural defects under 10% of wafer critical dimension. In conclusion, we confirm that SIRIUS can be available for the extreme ultraviolet mask inspection of hp 1X nm lines and spaces pattern.
With shrinking pattern size, mask 3D effects are estimated to become stronger, such as horizontal/vertical shadowing, best
focus shifts through pitch and pattern shift through focus. To reduce these mask 3D effects, we have proposed etched
multilayer EUV mask structure and have also reported on the fabrication process of etched multilayer EUV mask, in which
line and space mask patterning has been demonstrated. And by using etched multilayer EUV mask, the reduction of mask 3D
effects is experimentally demonstrated. In our previous study, we have shown etched multilayer EUV mask has enough
durability against chemical erosion in suitable cleaning process.
In this work, to meet the demands of different variation on pattern in etched multilayer mask, especially fabrication process
for sub-60nm pattern based on effective mirror width in dark-field exposure is studied. 60 nm pillar pattern on mask is
obtained using negative tone resist with keeping resolution of line and space pattern. We also examined CD characteristics 60
nm line and space pattern in consideration of effective mirror width. This work represents that etched multilayer EUV mask
is ready for dark-field exposure of 15 nm pattern in wafer.
With shrinking pattern size at 0.33NA EUV lithography systems, mask 3D effects are expected to become stronger, such
as horizontal/vertical shadowing, best focus shifts through pitch and pattern shift through focus. Etched multilayer EUV mask
structures have been proposed in order to reduce mask 3D effects. It is estimated that etched multilayer type mask is also
effective in reducing mask 3D effects at 0.33NA with lithographic simulation, and it is experimentally demonstrated with
NXE3300 EUV Lithography system. We obtained cross-sectional TEM image of etched multilayer EUV mask pattern. It is
observed that patterned multilayer width differs from pattern physical width. This means that effective reflecting width of
etched multilayer pattern is smaller than pattern width measured by CD-SEM.
In this work, we evaluate mask durability against both chemical and physical cleaning process to check the feasibility of
etched multilayer EUV mask patterning against mask cleaning for 0.33NA EUV extension. As a result, effective width can be
controlled by suitable cleaning chemicals because sidewall film works as a passivation film. And line and space pattern
collapse is not detected by DUV mask pattern inspection tool after mask physical cleaning that includes both megasonic and
binary spray steps with sufficient particle removal efficiency.
Recently, development of next generation extremely ultraviolet lithography (EUVL) equipment with high-NA
(Numerical Aperture) optics for less than hp10nm node is accelerated. Increasing magnification of projection
optics or mask size using conventional mask structure has been studied, but these methods make lithography cost
high because of low through put and preparing new large mask infrastructures. To avoid these issues, etched
multilayer EUV mask has been proposed. As a result of improvement of binary etched multilayer mask process,
hp40nm line and space pattern on mask (hp10nm on wafer using 4x optics) has been demonstrated. However,
mask patterns are easily collapsed by wet cleaning process due to their low durability caused by high aspect ratio.
We propose reducing the number of multilayer pairs from 40 to 20 in order to increase durability against
multilayer pattern collapse. With 20pair multilayer blank, durable minimum feature size of isolated line is
extended from 80nm to 56nm. CD uniformity and linearity of 20pair etched multilayer pattern are catching up
EUV mask requirement of 2014.
Recently, development of next generation extremely ultraviolet lithography (EUVL) equipment with high-NA
(Numerical Aperture) optics for less than hp10nm node is accelerated. While studying more than 0.45 NA,
incident angle distribution of EUV light irradiation to mask becomes larger. It induces degradation of exposure
margin to form horizontal line pattern (perpendicular to EUV light direction) because of large mask 3D effect. In
order to resolve this issue, we evaluate binary etched multilayer mask structure, unlike conventional stacked
absorber structure.
As a result of improvement of binary etched multilayer mask process, hp40nm line and space pattern on mask
(hp10nm on wafer using 4X optics) is demonstrated.
This result suggests the capability of high-NA EUVL with 6inch and 4X optics with new mask structure.
For EUVL mask with thinner absorber, it is necessary to make black border area in order to suppress the leakage of the EUV light from the adjacent exposure shots
Black border of etched multilayer is promising structure in terms of light-shield capability and mask process simplicity. However, EUVL masks with this structure do not have electrical conductivity between the inside and the outside of black border. Inspection area including device patterns belongs to the inside of the black border. In case that quality check for EUVL masks is performed with E-beam inspection, the area is floating. As a result, electrification to mask pattern occurs and causes degradation of E-beam inspection accuracy when the mask is inspected by E-beam inspection tool.
In this paper, we refine EUVL mask structure with black border of etched multilayer in order to improve electrical conductivity. We will show evaluation results of E-beam inspection accuracy, and discuss specifications of electrically conductive black border area.
Extreme Ultraviolet Lithography (EUVL) is a promising technology for the fabrication of ULSI devices with 20nm
half-pitch node. One of the key challenges before EUVL is to achieve defect-free masks. There are three main
categories of mask defects: multilayer defects which cause phase defects, absorber pattern defects, and particles during
blank/mask fabrication or mask handling after mask fabrication. It is important to manage multilayer defect because
small multilayer defects are difficult to be identified by SEM/AFM after mask patterning and can impact wafer
printing.
In this paper, we assess blank defect position error detected by 3rd generation blank inspection tool, using blank
defect information from blank supplier and 199nm wavelength patterned mask inspection tool NPI-7000. And we rank
blank defect in the order of projection defect size to multilayer in order to estimate blank defect printability. This
method avoids overestimating the number of potential killer defects that hardly be identified by SEM/AFM under the
condition that EUV-AIMS is not available.
It is important to control the defect level of the EUV lithography mask because of pellicle-less. We studied the resist
patterned wafer inspection method using EB inspection system.
In this paper, the defect detection sensitivity of EB inspection system is quantified using hp 32 nm line and space
pattern with about 5 nm LWR (Line Width Roughness). Programmed defects of 13 nm narrowing and 10 nm widening
have been detected successfully after the optimization of column and inspection condition. Next, the defects detected by
mask inspection system and EB wafer inspection system were compared and were in good agreement for printed killer
defects. In these results, EB inspection system is proved to be useful for EUV resist inspection.
Further, we evaluated the resist material damage by EB inspection irradiation and indicated the direction of reducing
the shrinkage.
Two EUVL masks were made using the compensation method for nonflatness of a mask; and the EUV1 was used to
evaluate the resulting overlay accuracy. For the same mask, the reproducibility of the intra-field overlay errors was better
than 1 nm (3σ) without linear components; and that of the flatness was better than 20 nm PV. In contrast, the overlay
errors were about 3 nm (3σ) for the two masks. The main cause of this degradation in overlay accuracy might be the
difference in mask flatness (~260 nm PV). Using overlay patterns corrected by the compensation method reduced the
overlay errors to about 2.5 nm (3σ). Although the compensation method produced only a small change, it definitely
improved the intra-field overlay of the EUV1. Furthermore, the EUV1 was used to evaluate the intra-wafer overlay for
23 shots. The single-machine overlay (SMO) was found to be better than 4.5 nm (Mean + 3σnonlinear), and the
mix-and-match overlay (MMO) between the EUV1 and an ArF immersion scanner (NSR-S610C) was about 20 nm
(Mean + 3σnonlinear). The main cause of the MMO errors might be the nonflatness of the mask and wafer chucks of the
EUV1. Thus, the chucks must be made flatter to reduce MMO errors. This work was supported in part by NEDO.
This paper describes the critical dimension (CD) accuracy of metal-layer patterns for the 15-nm logic node and beyond
replicated with model-based optical proximity correction, flare variation compensation, and shadowing effect correction.
The model fitting took resist shrinkage during CD measurements into account so as to reduce the modeling error. Since
sufficient accuracy was obtained for various patterns under the assumptions of device production, and since conventional
illumination could be used, it was possible to establish a design rule with few restrictions for the 15-nm node. For the 12-nm logic node, an SRAM pattern for a cell size of 0.0288 μm2 was fabricated using dipole illumination.
Advanced pre-production optics were used to assess the impact of flare on CD variation. Since chemical flare occurs in
SSR4, a top coating was used to prevent acid re-adsorption during the post-exposure bake. The flare due to the optics
was reduced to half that of conventional optics, and the CD variation due to flare was found to be predictable from the
point spread function of the projection optics. This means that the established concept of flare correction is usable with
advanced optics.
Phase defect printability and phase defect detection capability were investigated by exposure and inspection experiments,
and simulation analysis. A new test mask with absorber line patterns and programmed phase defects with sizes much
smaller than used in a previous work, was exposed using dipole illumination. Simulation results showed that printability
of phase defects at the wafer level depended not only on defects' sizes and their locations, or on the line widths of the
pattern structures to be printed, but also depended on the illumination conditions employed for pattern printing. Actinic
inspection test was also conducted using the programmed phase defect arrays formed on the test mask. Selete's upgraded
dark-field inspection tool was demonstrated to have its capability to detect a bump defect of 1.2 nm in height and 40 nm
in width at a detection probability of 90 % or larger. An extendibility of the actinic dark-field inspection to beyond half-pitch
22 nm node was also confirmed.
The key challenge before EUVL is to make defect-free masks, for which it is important to identify the root cause of
defects, and it is also necessary to establish suitable critical mask defect size for the production of ULSI devices. Selete
has been developing EUV mask infrastructures such as a full-field actinic blank inspection tool and 199nm wavelength
patterned mask inspection tool in order to support blank/mask supplier in reducing blank/mask defects which impact on
wafer printing. In this paper, by evaluating the printability of programmed phase defects and absorber defects exposed
by full-field scanner EUV1, we demonstrate that defect detection sensitivities of ABI (actinic blank inspection) and PI
(patterned mask inspection) are higher than that of WI (wafer inspection) in HP32nm. The evaluations were done by
comparing the detection sensitivities of full-field actinic blank inspection tool, 199nm wavelength patterned mask
inspection tool, and wafer EB inspection tool. And then, based on the native defect analysis of blank/mask, we
ascertained that actinic blank inspection and patterned mask inspection developed at Selete, are effective in detecting
killer defects both at the main pattern and at light-shield border area.
The impact of an EUV mask absorber defect with pattern roughness on lithographic images was studied. In order to reduce systematic line width roughness (LWR) of wafer printed patterns, the mask making process was improved; and in order to reduce random LWR, low line-edge roughness resist material and a critical dimension averaging method of multiple-exposure shots were introduced. Then, by using a small field exposure tool, a mask-induced systematic printed LWR was quantified and estimated at 32-nm half-pitch and 28-nm half-pitch. The measurement results of the critical mask absorber defect size were compared with the simulation, and the results were then discussed.
The key challenge before EUVL is to make defect-free masks hence it is important to identify the root cause of
defects, and it is also necessary to establish suitable critical mask defect size for the production of ULSI devices. Selete
has been developing EUV mask infrastructures such as a full-field actinic blank inspection tool and 199nm wavelength
patterned mask inspection tool in order to support blank/mask supplier in reducing blank/mask defects which impact on
wafer printing.
In this paper, we evaluate the printability of multilayer defects and of absorber defects exposed by a full-field scanner
EUV1, using full-field actinic/non-actinic blank inspection tool and 199nm wavelength patterned mask inspection tool.
And based on the results of native defect analysis of blank/mask, we ascertain that blank inspection with actinic is
necessary for mask fabrication in order to reduce the risk of missing phase defects, which hardly can be detected by
patterned mask inspection tool.
When a thinner absorber mask is applied to EUVL for ULSI chip production, it becomes essential to introduce EUV
light-shield border in order to suppress the leakage of EUV light from the adjacent exposure shots. Thin absorber mask
with light-shield border of etched multilayer adds to the process flexibility of a mask with high CD accuracy. In this
paper, we demonstrate the lithographic performance of a thin absorber mask with light-shield border of etched
multilayer using a full-field exposure tool (EUV1) operating under the current working condition of EUV source.
When a thinner absorber mask is practically applied to the extreme ultraviolet lithography for ultra large scale integration chip production, it is inevitable to introduce an extreme ultraviolet (EUV) light shield area to suppress leakage of the EUV light from adjacent exposure shots. We believe that a light-shield border of the multilayer etching type is a promising structure in terms of mask process flexibility for higher mask critical dimension accuracy. We evaluate the etching impact of the absorber and multilayer on the mask flatness and image placement change through the mask process of a thin absorber mask with a light-shield border of the multilayer etching type structure. We clarify the relation between mask flatness and mask image placement shift.
Extreme ultraviolet lithography (EUVL) is moving into the phase of the evaluation of integration for device fabrication.
This paper describes its applicability to the fabrication of back-end-of-line (BEOL) test chips with a feature size of hp 35
nm, which corresponds to the 19-nm logic node. The chips were used to evaluate two-level dual damascene
interconnects made with low-k film and Cu. The key factors needed for successful fabrication are a durable multi-stack
resist process, accurate critical dimension (CD) control, and usable overlay accuracy for the lithography process. A
multi-stack resist process employing 70-nm-thick resist and 25-nm-thick SOG was used on the Metal-1 (M1) and Metal-
2 (M2) layers. The resist thickness for the Via-1 (V1) layer was 80 nm. To obtain an accurate CD, we employed rulebased
corrections involving mask CD bias to compensate for flare variation, mask shadowing effects, and optical
proximity effects. With these corrections, the CD variation for various 35-nm trench and via patterns was about ± 1 nm.
The total overlay accuracy (|mean| ± 3σ) for V1 to M1 and M2 to V1 was below 12 nm. Electrical tests indicate that the
uses of Ru barrier metal and scalable porous silica are keys to obtaining operational devices. The evaluation of a BEOL
test chip revealed that EUVL is applicable to the fabrication of hp-35-nm interconnects and that device development can be accelerated.
In the fabrication of interconnect test chips with a half pitch of 35 nm, we used an EUV full-field scanner (EUV1)
for three critical layers: Metal 1, Via 1 and Metal 2. In this study, we focused on the Via-1 layer and investigated the
printing characteristics of 35-nm via-hole patterns. There are three types of major via-hole patterns; aligned, staggered,
and isolated. Simple optical proximity effect correction (OPC) and shadowing effect correction (SEC) were applied to
the mask patterns to reduce the iso-dense bias and anisotropy of hole shapes. Mask critical-dimension (CD) correction
enabled the fabrication of all three types of patterns with almost the same CD. A simulation analysis revealed the mask
error enhancement factor (MEEF) to be about 2.5, the exposure latitude to be about 18%, and the depth of focus (DOF)
to be about 100 nm for 35-nm via holes when the resist CD was 35 nm. The experimental results agree fairly well with
the simulation results. The intra-field CD uniformity of 35-nm via holes is 3.3 nm (3σ). The intra-field overlay accuracy
(Mean+3σ) between the Via-1 and Metal-2 layers is better than 15 nm. We used a multi-stacked resist to fabricate 35-nm
via holes in a low-k dielectric layer. Moreover, we fabricated interconnect test chips and measured their electrical
properties. The resistance of 32-nm vias is 12.4Ω, which meets the target of International Technology Roadmap for
Semiconductors (ITRS). The yield of 40k dense via chains was over 70%. The results demonstrate that EUV lithography
is useful for the fabrication of ULSI devices with a half pitch of 35 nm and beyond.
As regard to EUV-Mask natural defect printability evaluation, several methods have been employed in the past.
However, because of their inherent difficulties those methods have not been able to provide precise answers. In this
paper, we used two improved methods for the evaluation of EUV-Mask natural defect printability capable of providing
precise answers. One improvement involves marking of the defect locations which makes it easier to find the wafer
printed defects; the other method involves CD-averaging of multiple exposure shots that results in more quantifiable
answers.
Impact of EUV mask absorber defect with pattern-roughness on lithographic images was studied. In order to reduce
systematic line width roughness (LWR) of wafer printed pattern, mask making process was improved; and in order to
reduce random LWR, low line edge roughness (LER) resist material and a CD averaging method of multiple exposure
shots were introduced. Then by using a Small Field Exposure Tool (SFET), mask induced systematic printed LWR was
quantified and estimated at 32nm HP and 28nm HP. The measurement results of the critical mask absorber defect size
were compared with simulation; and the results are then discussed.
Multilayer defects embedded in EUV mask blanks are of primary concern in making usable mask because the multilayer
defects as small as 1.5 nm in height cause phase shifts and are most likely to be printable on wafers. To detect such phase
defects, we have developed an actinic (at wavelength) full-field EUV mask blank inspection tool equipped with dark-field
imaging optics. Inspection performance was demonstrated by a full-field mask blank inspection of a test mask blank
to detect its programmed phase defects and native phase defects. A potential of detecting phase defects among the
absorber patterns was also explored by inspecting masks with dot bump defects sitting among the absorber lines and line
bump defects perpendicular to the absorber lines. For the phase defect printability study, the test mask was exposed using
an EUV exposure tool (EUV1) at Selete. Simulation of projected image was also conducted using FDTD method.
Multilayer defect printability for varying location of the multilayer phase defects relative to the absorber line patterns
were evaluated
This work concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacturing based on accelerated development in critical areas, and the construction of a process liability (PL) test site that integrates results in these areas. Overall lithography performance is determined from the performance of the exposure tool, the printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 × 33 mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. The effect of flare on CD variation is a critical issue in EUVL, so flare is compensated for based on the point spread function for the projection optics of the EUV1 and aerial simulations that take resist blur into account. Production readiness of EUVL based on the integration of results in these areas is evaluated by electrical tests on low-resistance tungsten wiring. We find the PL test site to be very useful for determining where further improvements need to be made and for evaluating the production readiness of EUVL.
When thinner absorber mask is practically applied to the EUVL for the ULSI chip production, it is inevitable to
introduce EUV light shield area in order to suppress leakage of the EUV light from adjacent exposure shots. We believe
that light-shield border of multilayer etching type is promising structure in terms of mask process flexibility for higher
mask CD accuracy
In this paper, we evaluate etching impact of absorber and multilayer on mask flatness and image placement change
through mask process of thin absorber mask with light-shield border of multilayer etching type structure. And then, we
clarify the relation between mask flatness and mask image placement shift.
The effect of mask absorber thickness on defect printability in EUV lithography was studied. In case of very thin
absorber, when used for EUVL mask, it became necessary to set specifications for mask defects for the
manufacturability of ULSI devices because mask absorber thickness could impact defect printability. We prepared
programmed mask defects of LR-TaBN absorber with various thicknesses. We then investigated defect printability of
thin absorber mask with Small Field Exposure Tool (SFET) by comparing the data with simulation results.
This paper concerns the readiness of extreme ultraviolet lithography (EUVL) for high-volume manufacture based on
accelerated development in critical areas and the construction of a process liability (PL) test site that integrates results in
these areas. The overall lithography performance was determined from the performance of the exposure tool, the
printability obtainable with the resist, mask fabrication with accurate critical dimension (CD) control, and correction
technology for mask data preparation. The EUV1 exposure tool can carry out exposure over the full field (26 mm × 33
mm) at a resolution high enough for 32-nm line-and-space patterns when Selete Standard Resist 3 (SSR3) is used. Thus,
the test site was designed for the full-field exposure of various pattern sizes [half-pitch (hp) 32-50 nm]. The CD variation
of the mask was found to be as good as 2.8 nm (3σ); and only one printable defect was detected. The effect of flare on
CD variation is a critical issue in EUVL; so flare was compensated for based on the point spread function for the
projection optics of the EUV1 and aerial simulations that took resist blur into account. The accuracy obtained when an
electronic design automation (EDA) tool was used for mask resizing was found to be very good (error ≤ ±2 nm). Metal
wiring patterns with a size of hp 32 nm were successfully formed by wafer processing. The production readiness of
EUVL based on the integration of results in these areas was evaluated by electrical tests on low-resistance tungsten
wiring. The yield for the electrically open test for hp 50 nm (32-nm logic node) and hp 40 nm (22-nm logic node) were
found to be over 60% and around 50%, respectively; and the yield tended to decrease as patterns became smaller. We
found the PL test site to be very useful for determining where further improvements need to be made and for evaluating
the production readiness of EUVL.
The effect of mask structure with light shield area on the printability in EUV lithography was studied. When very
thin absorber on EUVL mask is used for ULSI application, it then becomes necessary to create EUV light shield area
on the mask in order to suppress possible leakage of EUV light from neighboring exposure shots. We proposed and
fabricated two types of masks with very thin absorber and light shield area structure. For both types of masks we
demonstrated high shield performances at light shield areas by employing a Small Field Exposure Tool (SFET).
The effects of mask absorber thickness on printability in EUV lithography was studied from the viewpoint of
lithographic requirements which can give high imaging contrast and reduce shadowing effect. From lithography
simulation, optimum thickness range of mask absorber (LR-TaBN) for exposure latitude was predicted, and the effect
of absorber thickness on MEF and H-V (Horizontal - Vertical) printed CD difference was determined using resist blur
model. From printability experiments with a Small Field Exposure Tool (SFET) and with high resolution resist,
optimum thickness of LR-TaBN absorber was demonstrated. When thinner absorber mask is employed in EUVL for
ULSI chip production, it becomes necessary to introduce EUV light shield area in order to suppress the leakage of EUV
light from neighboring exposure shots. Resist pattern CD change from the neighboring exposure shots was estimated
by lithography simulation.
In EUV lithography, particle-free handling is one of the critical issues because a pellicle is impractical due to its high
absorption. To investigate this subject, we have developed a mask protection engineering tool that allows various types
of tests to be carried out during the transfer of a mask or blank in air and in vacuum. We measured the number of particle
adders during the transfer of a mask blank in a dual-pod carrier and in an RSP200 carrier. We found that the number of
particle adders (>=46 nm PSL) to a mask blank in a dual pod is less than 0.01 over the whole process from taking the
blank out of the load port in air to putting it in the electrostatic chuck chamber in vacuum. Through various experiments,
the number of particle adders during any process using a dual pod was found to be very few and very stable. In contrast,
for a naked mask, many particle adders were found in large variations. Below one particle were added in over 80% of
experiments on a dual pod and in about 20% of experiments on a naked mask. Based on the test results, we can conclude
that the use of dual pod is an excellent particle-free transfer technique.
"Reticle protection during storage, handling and use" is one of the critical issues of EUV lithography because no
practical pellicle has been found for EUV reticles as yet. The front surface of an EUV reticle has to be protected from
particles larger than 20-30 nm to maintain the image quality on the wafer plane, and the backside also has to be protected
to maintain the flatness of the reticle chucked on an electrostatic chuck (ESC). In this paper, we are focusing on particles
on the backside of the reticle. If a particle lies between the reticle and the chuck, it has a strong impact on the flatness of
the reticle, and the wafer overlay is degraded by out-of-plane distortion (OPD) and in-plane distortion (IPD) due to the
particle1-5. From this point of view, we need to know the maximum permissible size of particles on the backside of the
reticle. MIRAI-Selete introduced an experimental setup that can measure the flatness of the chucked reticle in a vacuum.
An electrostatic chuck is installed in the vacuum chamber of Mask Protection Engineering Tool (MPE Tool)6, a reticle is
automatically carried from a reticle pod to the chuck in the tool. The flatness of the reticle can be measured by an
interferometer through a viewport underneath the chamber. We can measure the reticle flatness with 3-nm@rms
reproducibility using this setup. We report results of experimental evaluation about the relationship between the reticle
OPD, the size of particle and the chucking force of ESC.
Flare degrades critical-dimension (CD) control in EUVL, a promising technology for the 32-nm half-pitch node. To deal
with flare, high-quality projection optics in the exposure tool and flare variation compensation (FVC) technology with
proper mask resizing are needed. Selete has installed a small-field exposure tool (SFET) with the goal of assessing resist
performance. Due to the high-quality optics, the SFET allowed us to determine the required flare specification to be
6.1% or 6.6%, as calculated from the residual part of the low- or middle-frequency region, respectively. The flare level
was confirmed through experimental results and from calculations using the power spectral density (PSD) obtained from
the mirror roughness by the disappearing-resist method. The lithographic performance was evaluated using 32-nm-halfpitch
patterns in a new resist. The resist characteristics can be explained by modeling blur as a Gaussian function with a
σ of 8.8 nm and using a very accurate CD variation (< ~6 nm) obtained by taking into account the influences of mask
CD error and flare on evaluation patterns. Since FVC is needed to obtain flare characteristics that do not degrade the CD,
we used the double-exposure method to eliminate the influence of errors, including nonuniform dose distribution and CD
mask error. Regardless of whether there was an open area or not, there was no difference in CD as a function of distance
up to a distance of 20 µm. In addition, CD degradation was observed at distances not far (< 5 µm) from the open area. In
a 60-nm neighborhood of the open area, an 8-nm variation in CD appeared up to the distance at which the CD leveled
off. When the influences of resist blur and flare on patterns was taken into account in the calculation, it was found that
aerial simulations based on a rigorous 3D model of a mask structure matched the experimental results. These results
yield the appropriate mask resizing and the range in which flare has an influence, which is needed for FVC. This
research was supported in part by NEDO.
The impact of mask absorber properties on printability in EUV lithography was studied from the viewpoint of
lithographic requirements which can give high imaging contrast and reduce the shadowing effect. By using the
refractive indices of the elements and compounds employed as absorbers, their reflectivity on multilayer blanks, aerial
image on wafer plane and printed CDs depending on absorber thicknesses were simulated. This predicted an optimum
Ta-based absorber's thickness. Several patterned masks of LR-TaBN absorber with various thicknesses were prepared.
Each patterned mask was exposed with the newly developed small-field-exposure-tool (SFET). It was demonstrated
that optimized absorber thickness can, without loss of printability performance, reduce CD difference between
horizontal and vertical pattern that has been known to be caused by shadowing effect.
We have developed a mask protection engineering tool (MPE Tool) that simulates various types of tests during the
transfer of a mask or blank in air and in vacuum. We performed mask transfer experiments to investigate particle-free
mask handling techniques using the MPE and mask inspection tools. We measured the number of particles accumulated
during the transfer of the mask blanks. Less than 0.3 particles were added over a path from a load port (in air) to an ESC
chamber (in vacuum) and more than half the particles accumulated appeared during the pumping down and purging steps
in the load-lock chamber. Consequently, we consider that pumping down and purging are the most important steps for
particle-free mask handling.
We propose a new method of quality assurance for attenuated phase shifting mask (PSM) using the concept of the flexible mask specifications to extend the life of PSM [1]. The haze on PSM is a major issue for ArF lithography in semiconductor device manufacturing since it causes decline of device yield. PSM irradiated by ArF laser is periodically cleaned before haze is printed on wafer, which is a killer defect. Repetition of cleaning causes great changes of properties, i.e. phase, transmittance. Therefore, the number of times cleaning is performed has been limited by predetermined specifications based on ITRS. In this paper, relaxation of the pass/ fail criteria are studied as one solution to this limitation problem. In order to decide a suitable number of times for cleaning to be performed, we introduce the concept of flexible mask specifications, taking lithography margin into account.
Firstly, we obtained mask parameters before cleaning; these parameters were, for instance, phase, transmittance and CD. Secondly, using these parameters, we simulated images of resist pattern exposed on wafer and obtained exposure latitude at desired depth of focus. Thirdly, we simulated mask parameters and exposure latitude when the mask was cleaned several times and obtained correlation between number of times cleaning is performed and exposure latitude. And finally, we estimated suitable pass/ fail criteria of mask parameters and the maximum number of times cleaning should be performed for each mask at the standard exposure latitude. In the above procedure, the maximum number of times cleaning should be performed exceeded that determined in the case of conventional specifications based on ITRS.
We, MIRAI-Selete, started a new EUV mask program in April, 2006. Development of EUV mask handling technology is
one of the key areas of the program. We plan to develop mask handling technology and to evaluate EUV mask carriers
using Lasertec M3350, a particle inspection tool with the defect sensitivity less than 50nm PSL, and Mask Protection
Engineering Tool (named "MPE Tool"). M3350 is a newly developed tool based on a conventional M1350 for EUV
blanks inspection. Since our M3350 has a blank flipping mechanism in it, we can inspect the front and the back surface
of the blank automatically. We plan to use the M3350 for evaluating particle adders during mask shipping, storage and
handling. MPE Tool is a special tool exclusively developed for demonstration of pellicleless mask handling. It can
handle a mask within a protective enclosure, which Canon and Nikon have been jointly proposing1, and also, can be
modified to handle other type of carrier as the need arises.
An algorithm necessary to decide the optimum optical properties of a single-layer halftone (HT) mask has been established. This paper reveals the relations between the refractive index n and the extinction coefficient k, and thickness d, and describes how to select optimum films among various materials. It has been found that SiNx is a good material for a single-layer HT mask for I-line (365 nm) and KrF (248 nm). The lithographic performance of an I-line SiNx HT mask for grouped line and space (L&S) patterns under annular illumination has also been demonstrated.
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