3D NAND has become the mainstream technology to support bit growth of NAND Flash. The main challenge of 3D NAND is the increased level of wafer deformation as more layers are stacked vertically. This global deformation of the substrate leads to a significant degradation of overlay performance. One potential way to address this challenge is through bow compensation by wafer backside deposition. However, it turns out that standard backside processes sometimes do not improve overlay. This study investigates this phenomenon and explores how to counter high levels of wafer deformation in a way that overlay performance does not deteriorate. Scanner monitor wafers with etched reference marks have been modified to create a variety of global warp levels, covering a wafer bow range from +300μm (bowl shape) to -550μm (umbrella shape). Subsequently, several different backside deposition processes have been applied to these wafers. Flat reference wafers, warped wafers, and compensated wafers have been then measured on NXT scanners with different wafer tables. Non-linear overlay residuals of these wafers from about 1nm (flat reference wafers) to more than 30nm (uncompensated highly deformed wafers) have been measured. The obtained data reveal clear correlations between overlay, global wafer shape and backside deposition. A demonstration of the optimized overlay performance on wafers with large warpage values will be shown with a detailed analysis through absolute overlay metrology.
S. Steen, S. McNab, L. Sekaric, I. Babich, J. Patel, J. Bucchignano, M. Rooks, D. Fried, A. Topol, J. Brancaccio, R. Yu, J. Hergenrother, J. Doyle, R. Nunes, R. Viswanathan, S. Purushothaman, M. Rothwell
Semiconductor process development teams are faced with increasing process and integration complexity while the time between lithographic capability and volume production has remained more or less constant over the last decade. Lithography tools have often gated the volume checkpoint of a new device node on the ITRS roadmap. The processes have to be redeveloped after the tooling capability for the new groundrule is obtained since straight scaling is no longer sufficient. In certain cases the time window that the process development teams have is actually decreasing. In the extreme, some forecasts are showing that by the time the 45nm technology node is scheduled for volume production, the tooling vendors will just begin shipping the tools required for this technology node.
To address this time pressure, IBM has implemented a hybrid-lithography strategy that marries the advantages of optical lithography (high throughput) with electron beam direct write lithography (high resolution and alignment capability). This hybrid-lithography scheme allows for the timely development of semiconductor processes for the 32nm node, and beyond.
In this paper we will describe how hybrid lithography has enabled early process integration and device learning and how IBM applied e-beam & optical hybrid lithography to create the world's smallest working SRAM cell.
IBM Research has developed a time resolved imaging technique, Picosecond Imaging Circuit Analysis (PICA), which uses single photon events to analyze signals in modern microprocessors on a picosecond time scale. This paper will describe the experimental setup as well as the data management software. A case study of a particularly hard debug problem on a state of the art microprocessor will demonstrate the application of the PICA method.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.