Tight control of critical dimensions (CDs) of integrated circuit (IC) is required to achieve desired circuit performances, and getting more and more important as the IC CD shrinks. Phenomena and solutions of inter-field and intra-field CD errors have been widely studied for years. One of the well-known intra-field CD errors is so called the developer micro-loading effect due to the different pattern density loadings across the exposure field, in the other words, the more different the pattern density is, the more CD errors it would be expected. Some of the circuit layouts, e.g. thick gate oxide layers of dual gate oxide processes, and gate layers of embedded memory products, have this kind of across field pattern density concerns because of the different pattern density areas. Some researches showed that eliminating the by-products during the development process could reduce the developer micro-loading effect. With a multi-step development process (Puddle-Static Development-Dry-Puddle-Static Development-Rinse/Dry), the by-products can be removed and achieve a better CD uniformity. In this paper, optimization of the first puddle time in the multi-step development process is found to be the most critical to achieve uniform intra-field CDs. The purpose of the first puddle step is not only to remove the by-products but also to control the influence of the by-products to achieve uniform intra-field CDs. Once most of the by-products generated during the whole development process were carried away by the first puddle step, the optimum static Dev. time is needed to obtain the minimum intra-field CD difference. However, different photo-resists with different chemical formulations are expected to have identical optimum puddle time due to different chemical reactions of each by-product species, e.g. i-line PRs vs DUV PRs, or annealing type DUV PRs vs acetel type DUV PRs. These comparisons will be explained in details in this paper. Finally, the source of the by-products during the developer process was also identified to verify the validation of the multi-step developer process.
Optical resolution limit is one of the concerns for exposure tool selection. ArF lithography tools are the first choice for critical layers of 90 nm node with pitches narrower than 280 nm. However, high cost of ArF tools and photoresists make IC manufacturers try to seek for alternatives. Extension of KrF lithography has been widely discussed. For mass production of 130 nm node, KrF lithography has been pushed hard to achieve 160 nm contact holes with 320 nm pitch. In this paper, printing of via holes with the minimum pitch of 280 nm has been demonstrated with a special designed multi-pole aperture and high NA KrF lithography. With these illumination settings, reasonable process windows through all the pitches can be achieved for mass production of 90 nm node logic devices. Multi-pole illumination aperture settings are critical for balancing through-pitch process margins. Forbidden regions should not be found with optimum multi-pole illumination settings. In other words, the adequate combinations of multi-pole sizes and locations can minimize the forbidden proximity behavior and also keep the aerial imaging contrast balance through all the pitches. Mask bias is another factor to enlarge the common process windows. The process margin depth of focus (DOF) and mask enhanced error factor (MEEF) are investigated with various multi-pole settings and mask biases. Simulation works have been done for fine-tuning of the multi-pole aperture to reduce through pitch MEEF and optimize mask biases.
Due to the existing problems and delay of 157nm lithography tool, extension of the ArF (193nm) lithography process with resolution enhancement techniques (RET) should be considered for the 65nm generation lithography and beyond. The mature double-exposure lithography process based on dark-field alternating phase-shift mask (PSM) is one of the promising RET candidates, which is proven to be one of the production-ready strong phase-shifting techniques for current and future IC generations. In this paper, poly gate patterning with the minimum pitch of 160nm has been demonstrated with high numeric aperture (NA) and small partial coherence of ArF lithography along with a dark-field alternating PSM. For poly gate patterning of 65nm generation, optimum illumination settings are found for minimum pitch of 160nm. Through-pitch common process windows for gates with 65nm after-development-inspection (ADI) critical dimension (CD) at minimum pitch of 160nm can be reached larger than 0.30um depth of focus (DOF), which can be used for 65nm node production. Through-pitch proximity can be compensated by optical proximity correction (OPC). Line edge roughness (LER) can be improved a little by this dark-field alternating PSM technique. LER is found of strong aerial image contrast dependency. Shifter width is also chosen as optimum value to obtain the largest process windows and minimize the phase conflicts. 193nm Hi-NA or liquid immersion lithography is suggested to push the alternating PSM resolution limitation.
A small notch or foot existing at the bottom of a polysilicon gate is a common issue for etching processes. The small notch or foot could have a major impact on the length of the polysilicon gate, and the performance of the device would then be impacted significantly, especially for cutting-edge devices. This paper demonstrates the capability of a spectroscopic ellipsometry based profile technology, SpectraCD, as a new metrology tool to monitor polysilicon gate process at 130 nm and 90 nm nodes. Firstly, the capability of SpectraCD as a metrology technology was studied, including dynamic precision and CD correlation. Dynamic precision in the range of 0.1~0.4 nm was demonstrated repeatedly in this study. CD correlation with CDSEM also showed a very linear result. R-squared values of ~0.99 are presented. Secondly, by comparison with images from cross-sectional SEM (XSEM) and TEM (XTEM), it has been proved in this study that SpectraCD can consistently flag different profile excursions of polysilicon gate, e.g., small notching, footing, or undercut. The size of the footing or notch reported by SpectraCD shows a linear correlation with the size extracted from XTEM images, which demonstrates quantitatively SpectraCD capability for detecting profile excursions. Finally, linear correlation between the bottom CD from SpectraCD and the gate lengths determined from electrical test (Lcap) will be presented.
There are many works on extension of KrF lithography for 90 nm logic generation, especially for those back end of line (BEOL) layers. High cost and immaturity of ArF tools and photoresists are the major factors that make IC manufacturers try to seek for the possibility of KrF lithography. For mass production of 130 nm node, KrF lithography has been pushed hard to achieve 160 nm contact holes with 320 nm pitch. However, with pushing KrF lithography further, printing of 140 nm via holes with the minimum pitch of 280 nm was required by the tight 90 nm design rules. Optimizing illumination settings is one way to obtain reasonable process windows through all the pitches for mass production of 90 nm node logic devices, and maintaining exposure tools in good conditions is the other. The control of pattern deformation becomes more and more significant when the critical dimension is drove to the limit. In this paper, oval shaped via holes were found for symmetrical pitch patterns. Lens aberration and synchronization errors of scanners are always the first considerations when pattern deformation happened. But after investigations, improvement of via pattern deformation control has been demonstrated by reducing the low frequency resonance of scanner projection lens. The via deformation is investigated in combination of different scanning and stepping speed of scanner stages, which will cause different amplitude of projection lens resonance. Low frequency region of projection lens resonance spectra showed less amplitude while scanning or stepping speed was slow. Pattern distortion was also reduced as amplitude of low frequency project lens resonance went low. Common process window was then improved due to the elimination of via cd difference between x and y direction. With this improvement, reasonable process window (DOF ~ 0.3 um) can be achieved for mass production of 90 nm devices on KrF lithography tools.
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