Advanced semiconductor devices target sub-2nm on-product overlay (OPO) and manufacturers utilize dense overlay (OVL) sampling and non-zero offset (NZO) control to enable such strict performance. Accurate optical OVL metrology systems with fast move-and-measurement (MAM) utilized at the after-develop inspection (ADI) step are required to support this OPO trend. This work presents an innovative Artificial Intelligence (AI) based, ultra-high-speed, overlay target focusing and centering approach on imaging-based overlay (IBO) measurements in the ADI step. The algorithm uses pre-trained image features and a deep learning model. The algorithm allows the measurement of every site across the wafer in its best centering and contrast focus position and thus overcomes intra-wafer process variations and enhanced measurement accuracy. The data will include results from multi-lot advanced DRAM process with basic performance analysis such as total measurement uncertainty (TMU), tool-to-tool matching (TTTM) and additional key performance indicators (KPIs).
With the continuous shrinking of semiconductor device nodes, the reduction of on-product overlay (OPO) becomes extremely critical for high-yield IC (Integrated Circuit) manufacturing. This requires accurate overlay (OVL) process control which can be better achieved by using an optimized OVL target design and a more advanced metrology platform. The novel rAIM® imaging-based-overlay (IBO) target, which has a grating-over-grating structure with significantly smaller pitch sizes as compared to the standard advanced-imaging-metrology (AIM®) target, can improve OVL measurement accuracy by adopting a more device-compatible design with high Moiré sensitivity. This paper demonstrates the advantages of rAIM targets by comparing and quantifying their performance to standard AIM targets through key parameters including raw OVL, residuals, precision, and total measurement uncertainty (TMU). We also present the performance of rAIM targets on different OVL metrology platforms. We conclude that with an optimized target design and an advanced OVL measurement platform, rAIM targets can be an ideal overlay metrology solution for advanced dynamic random-access memory (DRAM) devices.
The semiconductor industry continually evaluates new materials to improve the process or minimize product variability, which could create measurement challenges for metrology tools in the visible and near-infrared (NIR) spectrum. Opaque materials (i.e., ‘hard masks,’ ‘HM’) are placed in between the resist (i.e., inner layer) and process (i.e., outer layer or underlying layer) in 3D NAND or DRAM processes to control the etch of high aspect-ratio structures to maximize product yield. However, longer wavelengths (e.g., IR WL) may be required to penetrate and properly view the underlying process layer and measure OVL accurately. In this work, longer wavelengths will be evaluated to improve measurement accuracy and keep up with the increasing use of opaque materials, which is expected to increase in future nodes. We will review the benefits of IR WL to OVL measurement accuracy by quantifying the OVL residuals, contrast precision (CP), and total measurement uncertainty (TMU) on multiple DRAM and 3D NAND critical layers.
As the semiconductor industry rapidly approaches the 3nm lithography node, on-product overlay (OPO) requirements have become tighter, which drives metrology performance enhancements to meet the reduction in overlay (OVL) residuals. The utilization of multiple measurement wavelengths in Imaging- Based Overlay (IBO) has increased in the past few years to meet these needs. Specifically, the color per layer (CPL) method allows for optimizing the OVL measurement conditions per layer, including focus, light, wavelength (WL), and polarization customization which enhance the metrology results. CPL is applicable for multiple technology segments (logic, foundry, DRAM, 3D NAND), relevant for different devices (DRAM high stack layers, NAND channel holes, etc.), and can work well for both thin and thick layers for standard and EUV lithography processes. In this paper, we will review the benefits of CPL for multiple DRAM and NAND critical layers. We will describe how CPL can contribute to measurement accuracy by quantifying the OVL residual reduction in comparison to single-wavelength (SWL) measurement conditions.
Over the past few years, on product overlay (OPO) challenges have become serious yield limiters for the latest technology nodes, requiring new and innovative overlay (OVL) metrology solutions. OVL metrology systems must have excellent measurability capabilities to cover as many different layers as possible, minimize any systematic contribution to measured OVL and demonstrate low residuals and high correlation to AEI SEM and AEI in die overlay (IDO). OVL metrology system manufacturers are required to introduce new target designs, tool hardware (HW) and advanced algorithms to keep up with said challenges. The paper will present optical OVL solutions per segment: foundry, logic, DRAM, and 3D NAND. We will review various new technologies developed in the last year that improve the OVL measurement systems’ performance to meet the above challenges. We will see how the new innovative targets improve measurability and accuracy on imaging-based overlay (IBO) and scatterometry-based overlay (SCOL®). Then, we will review new hardware components designed to improve measurability and overall fleet matching. Lastly, we will discuss how advanced machine learning (ML), multi-wavelength (MWL) and signal-weighting algorithms improve measurability, accuracy, and overall measurement performance.
Semiconductor manufacturers are increasingly motivated to reduce overlay (OVL) target size. The scribe line area is in high demand, especially as width reduction efforts persist. Furthermore, since overlay control challenges require a higher sampling density, there is a growing need to place ultra-small targets inside the active chip, especially for devices with a large area. One of the main challenges of this new reality is producing smaller cell (grating) sizes to form smaller overlay targets, while maintaining compatible measurements to the standard target size of the same design. To overcome this challenge on typical scatterometry-based overlay (SCOL®) targets, we describe a method developed to perform the preliminary evaluation on a standard cell size of 8μm. This method selects a scalable setup by predicting performance on a 3-5um cell with the same target design (TD) parameters. This allows chipmakers to qualify the OVL measurement during process development on standard size targets, with the confidence that the optimized measurement conditions will be carried over to the smaller targets, saving time and real estate. However, even for scalable designs, target size reduction necessarily forces some size-performance tradeoffs: factors that are negligible for a standard target size can have significant impact on a scaled-down version of the same target design. In this paper we analyze these factors, show how they relate to measurement indicators, and present a method to apply such indicators toward setup selection. For each setup candidate this method can provide predicted performance and measurability as a function of cell size, a powerful tool for target area reduction.
As 3D NAND devices increase memory density by adding layers, scaling and increasing bits-per-cell, new overlay (OVL) metrology challenges arise. On product overlay (OPO) may decrease for critical thick layers such as thick deck-to-deck alignment, whereas high aspect ratio (Z-axis) structures introduce stress, tilt and deformation that require accurate and robust OVL measurements. Advanced imaging metrology (AIM®) targets, that consist of two side-byside periodic gratings in the previous and current layers, are typically used to measure OVL with Imaging Based Overlay (IBO) metrology systems. In this paper, we present a new approach that utilizes the Talbot effect in AIM to produce multiple contrast planes along the Z-axis, which enables a common focus position for both layers at a similar focus plane, resulting in improved measurement robustness. We will present Talbot effect theory, target design steps by metrology target design (MTD) simulator, actual measurement results on an advanced 3D NAND device and conclusions for such targets.
On Product Overlay (OPO) control is a critical factor in advanced semiconductor manufacturing. As feature sizes become smaller, OPO budgets become tighter, leaving less room for overlay (OVL) measurement inaccuracy. Over the last few years, overlay metrology’s focus has shifted inwards, towards accurate measurement conditions, as we aim to capture ever-smaller process and scanner variations. One method used to break down the OPO error budget is combining one or more accuracy flags and correlating them to various process impacts. Analyzing the overlay accuracy signature generated by accuracy flags can be useful for data validation, inspection and correlation to different processes and metrologies. In this paper, an extensive OVL accuracy experiment demonstrates the use of this new method. First, the method is applied to several wafers designed with intentional process variation, including variations in etch duration, Chemical Mechanical Polishing (CMP) duration, amorphous silicon (a-Si) thickness and titanium nitride (TiN) thickness. OVL results from the experimental wafers are compared with results from the reference (nominal) wafer.
On product overlay (OPO) challenges continue to be yield limiters for most advanced technology nodes, requiring new and innovative metrology solutions. In this paper we will cover an approach to boost accuracy and robustness to process variation in imaging-based overlay (IBO) metrology by leveraging optimized measurement conditions per alignment layer. Results apply to both DUV and EUV lithography for advanced Logic, DRAM, 3D NAND and emerging memory devices. Such an approach fuses multi-signal information including Color Per Layer (CPL) and focus per layer. This approach with supporting algorithms strives to identify and address sources of measurement inaccuracy to enable tight OPO, improve accuracy stability and reduce overlay (OVL) residual error within the wafer and across lots. In this paper, we will present a theoretical overview, supporting simulations and measured data for multiple technology segments. Lastly, a discussion about next steps and future development will take place.
In the latest 3D NAND devices there is a larger focus on measurement accuracy control, coupled with more traditional minimization of Total Measurement Uncertainty (TMU). Measurement inaccuracy consumes an increasingly significant part of the overlay (OVL) budget, requiring control and optimization.
In this paper we will show the improvement in imaging OVL measurement accuracy using wave tuning (WT) capability combined with advanced algorithms to address 3D NAND process challenges. In addition to new OVL target designs that take advantage of WT capability, we also demonstrate improvement in OVL model residuals through optimization of measurement bandwidth, focus position and number of grab frames. Improvements in precision and tool-to-tool matching are also realized through both optimization of the region of interest (ROI) and splitting measurement areas using a dual-recipe technique.
Tool induced shift (TIS) is a measurement error attributed to tool asymmetry issues and is commonly used to measure the accuracy of metrology tools. Overlay (OVL) measurement inaccuracy is commonly caused by lens aberration, lens alignment, illumination alignment and asymmetries on the measured target. TIS impacts total measurement uncertainty (TMU) and tool-to-tool matching, and TIS variation across wafer can account for inaccuracy, if not fully corrected, as it depends on the incoming process condition. In addition, both lot-to-lot and wafer-to-wafer process variation are influenced by TIS in terms of overlay performance, which also includes metrology tool-to-tool efficiency in terms of throughput. In the past, TIS correction was only done using a small sampling, resulting in additional error in the measurement which was not corrected. Hence, a new methodology is explored to improve overlay measurement accuracy by Modeled-TIS (M-TIS). This paper discusses a new approach of harnessing Machine Learning (ML) algorithms to predict TIS correction on imaging-based overlay (IBO) measurements at the after-develop inspection (ADI) step. KLA’s ML algorithm is trained to detect TIS error contributors to overlay measurements by training a model to find the required TIS correction for one wafer. This information, along with additional accuracy metrics, is then used to predict the TIS for other wafers, without having to actually measure the wafers. In this paper, we present the results of a case study focusing on DRAM and 3D NAND production lots.
As the semiconductor industry rapidly approaches the 3nm lithography node, on product overlay (OPO) requirements have become tighter and as a result, residuals magnitude requirements have become even more challenging. Metrology performance enhancements are required to meet these demands. Color Per Layer (CPL) is a unique imaging overlay metrology approach that enables the measurement of each layer with individually-optimized wavelength and focus position. CPL allows the user to custom-define the most suitable conditions per layer, thereby ensuring optimal performance. Imaging-based overlay (IBO) utilizes CPL in order to overcome inaccuracies due to interactions between bottom and top layers. These layers are fundamentally different in that the top grating is usually the photoresist layer, but the bottom grating can be any process layer. Therefore, optimizing the conditions for each layer will maximize measurement accuracy. KLA’s Archer™ 700 metrology tool addresses these metrology challenges by putting CPL to use, where the Wave Tuner (WT) allows the user to select a specific wavelength. This paper presents this novel CPL approach and discusses its reduction in OPO and contrast, and reviews use cases from DRAM and 3D NAND. We will present the results from these case studies, focusing on SK Hynix DRAM production wafers.
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