Domain-wall (DW) logic holds promise for compact and energy-efficient logic circuits. Indeed, fast DW motion driven by spin-orbit torque (SOT) and the Dzyaloshinskii-Moriya interaction (DMI) in magnetic/heavy-metal multilayers led to the experimental demonstration of current-driven DW logic circuits by magnetic imaging. Advancing towards applications, we present DW devices with electrical write/read using a magnetic tunnel junction (MTJ) stack with a hybrid free layer on 300-mm wafers. The first layer provides efficient spin-transfer torque (STT) and high tunneling magnetoresistance (TMR), while the second layer enables fast SOT-driven DW motion. It allows full electrical control of nanoscale DW devices, involving write/read at input/output MTJs and SOT-driven propagation between them. Finally, to alleviate challenges in current-driven DW motion, we present a concept of chirally coupled MTJs through DMI. This enables current-free information processing in compact inverter and minority gates.
Current-induced torques enable fast and efficient control of the state of magnetic tunnel junctions (MTJ). While switching dynamics has been extensively studied in spin transfer torque (STT) driven MTJ devices, less is known about the transient dynamics and actual reversal speed of individual switching events induced by spin-orbit torques (SOT). Our real-time single-shot measurements reveal that SOT switching unfolds by a stochastic two-step process involving the nucleation and propagation of a reversed domain. Timescales and statistical distributions of these processes differ significantly when compared to switching by STT. The stochastic nature of the switching dynamics can be minimized by the combined action of SOT, STT, and the voltage control of magnetic anisotropy, resulting in reproducible sub-nanosecond switching with a distribution of switching onsets and durations approaching 0.1 ns.
In this paper, patterning challenges that led to the fabrication of a first Spin Torque Majority Gate (STMG) device are explored. We have highlighted key process module developments from the Magnetic Tunnel Junctions (MTJs) pillar patterning to dual damascene scheme wiring module. Spin devices such as STMG have already been proposed as a replacement for conventional CMOS transistors. The main challenge to their experimental demonstration remains the successful fabrication of connected MTJs through a ferromagnetic layer, allowing spin transport across the gate. We propose a new etching approach utilizing Ion Beam Etching (IBE), to be able to pattern the MTJs with high precision and with less damage to the magnetic layers. Furthermore, we have introduced Electron-beam lithography to further scale down the device geometries. This development paves the way towards a fully integrated STMG device for Spin Logic applications.
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